Monte P. Tull

Digital micromirror device for optical scanning applications

Recent mechanical and nonmechanical optical scanning devices do not meet the fast scanning requirements for contemporary and emerging applications and can only steer optical beams over relatively narrow angles. A variety of important applications require fast optical scanning devices that can steer laser beams rapidly to an arbitrary location and with no moving parts. We introduce a new optical scanning technique that can be used to collimate and steer optical beams for precision alignment in either 2-D free-space optical (FSO) communications links or image scanners. This nonmechanical technique is capable of rapidly redirecting the optical beams to arbitrary locations without greatly sacrificing other parameters such as aperture size, efficiency, and scanning range. A digital micromirror device (DMD) beam-steering system was successfully demonstrated and exhibited better performance results when compared with other available systems.

Phase-Guided Scheduling on Single-ISA Heterogeneous Multicore Processors

Single-ISA heterogeneous (also known as asymmetric) multicore processors offer significant advantages over homogenous multicores in terms of both power and performance. Power-efficient cores can be paired with higher-performance cores to achieve advantageous power/performance tradeoffs. Unfortunately, such processors also create unique challenges in effective mapping of processes to cores. The greater the diversity of cores, the more complex this problem becomes. Previous scheduling approaches sample performance while permuting the schedule across each type of core each time a change in application behavior is detected. However, approaches that require frequent sampling of the performance of threads (or combinations of threads) on each core may be impractical. We propose scheduling threads on a heterogeneous multicore processor using not just the detection of a change in program behavior or phase, but instead an identification and recording of these phase behaviors. We highlight the correlation between the execution phases of an application and the performance of those phases on any particular core type. We present mechanisms that exploit this correlation between program phases and appropriate scheduling decisions and demonstrate near optimal mapping of thread segments to processor cores can be done without frequently sampling the performance of each thread on each processor core type.

Configuration steering for a reconfigurable superscalar processor

An architecture for a reconfigurable superscalar processor is described in which some of its execution units are implemented in reconfigurable hardware. The overall configuration of the processor is defined according to how its reconfigurable execution units are configured. An efficient micro-architectural solution to configuration management is presented that effectively steers the current processor configuration toward a configuration that is well matched with the execution unit requirements of instructions being scheduled for execution. The approach first selects the best matched among four steering configurations based on the number and type of execution units required by the instructions. One of the steering configurations is dynamically defined as the current configuration; the other three are statically predefined. Once a steering configuration is selected, portions of it begin loading on corresponding reconfigurable execution units that are not busy. The active configuration of the processor is generally the overlap of two or more steering configurations.

The implementation of an efficient and high-speed inner-product processor

A novel, high-performance fixed-point inner-product processor based on a redundant binary number system is presented. The proposed scheme decreases the number of partial products to 50%, compared to other methods, while achieving better speed and area performance and providing pipeline extension opportunities. When modified Booth encoding is used, partial products are reduced by almost 75%, thereby significantly reducing the multiplier addition depth. The design is applicable for digital signal and image processing applications that require inner-product arithmetic, such as digital filters, correlation and convolution. The proposed design is well suited for VLSI implementation, and it can also be embedded as an inner-product core inside a DSP processor or FPGA-based processor.

A Large 3D Swept-Volume Video Display

The demand and applications for three-dimensional (3D) display systems is rapidly increasing. Many innovative, truly 3D display technologies have recently been developed, particularly those in the category of volumetric displays. However, currently no large format displays can produce true 3D images. They are either two-dimensional (2D) displays and represent the third dimension using well known techniques of shading and shadowing, or they are not full parallax displays and require the viewer to wear special head gear. There are many applications for large, truly 3D displays including billboards, kiosks, theaters, medicine, radar imaging, military and entertainment. To meet these growing applications, we introduce a large swept-volume display (LSVD) that is capable of displaying full-motion 3D video. The LSVD is comprised of several rotating panels; each rotating panel contains several image panes, and each image pane contains a field-programmable gate array (FPGA) that controls light-emitting diodes (LEDs). The rotating panels fill the volume of a cylinder that makes up a column of the display. The derivation of parameters for the arrangement of columns and the overlapping regions between the columns is also presented. In addition, an image partitioning algorithm that partitions the full image into the LSVD columns is provided along with the original circuit designs of a rendering algorithm for providing real-time, full-motion 3D video for SVDs.

Distributed ITS control and the Oklahoma virtual TMC

Practically all major metropolitan and large scale modern intelligent transportation systems have a centralized traffic management center (TMC) at their logical and functional core. The TMC provides control, coordinates system wide communications, and typically serves as a common hub from which multiple agencies plan and execute coordinated incident responses. Early in the development of the Oklahoma statewide ITS, it became clear that the costs associated with building and operating a large, centralized TMC would be prohibitive. An alternative design strategy emerged built around a distributed peer-to-peer network of low-cost ITS consoles based on desktop PCs equipped with innovative software and special hardware to support efficiently handling multiple video streams simultaneously. This has led to a geographically distributed, fault-tolerant communications and control system where the desirable functionality of a large centralized TMC is realized by a virtual TMC that enables the stakeholder agencies to remain physical located in their current facilities around the State. In this paper, we provide an overview of the system architecture as it has evolved through the first quarter of 2009 and highlight some of the recently developed system enhancements.

Thread scheduling for heterogeneous multicore processors using phase identification

Heterogeneous multicore processors (HMPs) offer promise for significant efficiency improvement. Power-effcient cores can be paired with higher performance cores in an HMP to achieve a beneficial design in terms of both power and performance. However, such processors produce challenges in the effective mapping of threads to cores. An application could have very different behavior and performance when executing on cores of different types. The behavior of typical applications also vary with their phases of execution. Thus, the type of core providing the best performance for an application may depend on the current phase. In this work, we highlight the correlation between execution phases of an application and the performance of those phases on particular core types. We propose mechanisms that identify program phases, exploit the performance behavior of these phases to make effective scheduling decisions, and reuse the result of these scheduling decisions on future occurrences of the same program phases.

Prediction aggregation of remote traffic microwave sensors speed and volume data

Short term traffic speed and volume prediction is an important component of well developed Intelligent Transportation Systems and Advanced Traveler Information Systems. In this paper, we examine the use of polled Remote Traffic Microwave Sensors as a data source for aggregate traffic predictors. Clock skew and data loss due to network transience pose significant challenges to integrating polled data into such a predictive system. To overcome these, we present a new interpolation and evaluation scheme for data regularization and predictor generation. A method for evaluating the validity of the test sets is proposed and illustrated in a case study using an aggregate predictor with real traffic sensor data acquired in Oklahoma City.

Selection of instruction set extensions for an FPGA embedded processor core

A design process is presented for the selection of a set of instruction set extensions for the PowerPC 405 processor that is embedded into the Xilinx Virtex family of FPGAs. The instruction set of the PowerPC 405 is extended by selecting additional instructions from the full 32-bit PowerPC instruction set architecture (ISA), of which the PowerPC 405 ISA is a subset. The selected instructions are supported in hardware using the reconfigurable resources of the FPGA. The proposed design process gathers execution statistics for a target application through profiling or simulation. These statistics are then used to estimate the speedup that would be achieved if selected instructions from the full PowerPC ISA are added to the ISA of the PowerPC 405 processor. An experimental study of two embedded benchmarks show significant speedup when this approach is used to extend the PowerPC 405 processor to support various floating-point operations through the use of floating-point cores developed by QinetiQ.

Multiplierless implementations of adaptive FIR filters

Implementations of adaptive filters using field programmable gate arrays require the ability to change the coefficient values of the filter based on the adaptation algorithm. Multiplierless filter designs rely on a priori knowledge of the coefficient values to implement the filter using hard-wired shifts and additions. We describe a multiplierless approach to adaptive filter implementation that reduces the complexity from quadratic to linear in the number of bits.