Moohong Lee

A Novel SIR to Channel-Quality Indicator (CQI) Mapping Method for HSDPA System

To support very high data rate services that require higher system capacity, the high speed downlink packet access (HSDPA) was proposed in the UMTS standard. One of key techniques supporting the HSDPA services is the adaptive modulation and coding (AMC) in which the modulation scheme and the coding rate are adaptively changed to match the current channel condition reported by the user equipment (UE). Therefore, the mapping between the channel quality indicator (CQI) and signal to interference ratio (SIR) is closely related to the accuracy of AMC and the performance of HSDPA. This paper proposes a novel SIR to CQI mapping method that satisfies the 3GPP requirements. In order to verify the performance of the proposed mapping method, we implemented the link-level simulator which is composed of all the physical layer blocks depicted in the 3GPP standard. With the proposed mapping method, we show that UE can report the exact channel condition and the system can yield performance exceeding the requirements in the 3GPP technical specification.

An Efficient Hardware Simulator for the Design of a WCDMA Interference Cancellation Repeater

An efficient hardware simulator for the design of a WCDMA interference cancellation repeater (ICR) is presented. The ICR, which is composed of a digital interference canceller and analog parts, is a time-varying system that reacts to a time varying input signal. The design of the digital interference canceller is time-consuming due to the need for many iteration cycles of debugging, tuning, and performance verification. Furthermore, its performance, which is represented by the error vector magnitude (EVM) and the output power spectrum, can be verified only after it is implemented on a digital board, integrated into the repeater hardware with analog parts, and hooked up with expensive test equipment. Hence, a special computerized simulator is needed for fast and efficient verification of the interference cancellers design. The simulator consists of a signal generator, which emulates a base station, the ICR with an interference canceller, a feedback channel that models wireless fading channels, and a receiver that measures the EVM of the ICR. The accuracy of the simulator is verified by showing that the EVM and the output power spectrum of a reference interference canceller measured on this simulator match well within an error range of less than 8% with the corresponding values measured on the repeater hardware. The usefulness of the simulator is also confirmed by simulating the EVM performance of the ICR under various multipath fading channel conditions.

A software-based receiver running on a single DSP for terrestrial digital multimedia broadcasting

This paper presents the design and implementation of a software (SW)-based receiver running on a single digital signal processor (DSP) for terrestrial digital multimedia broadcasting (TDMB). Implementing the functions of the physical layer such as synchronization and channel decoding as well as codec decoders for a TDMB receiver in software running a DPS raises numerous design and implementation issues. We present solutions to these issues including an efficient software receiver structure, efficient algorithms with low complexity, real-time scheduling, reduction of the execution cycle number, and data transfer and communication between function blocks in the receiver, with a focus on the physical layer. The SW-based TDMB receiver developed in the present work can change and upgrade its functions and adapt to new standards. The performance of the implemented receiver was verified through successful decoding of live audio and video signals.

Processing speed improvement based on an efficient symbol decoding structure in a T-DMB software baseband receiver

Unlike the computationally intensive channel decoding part in the T-DMB baseband receiver, the symbol decoding part consists of many computationally not-intensive function blocks handling complex data. Hence, if implemented in software running on a digital signal processor (DSP) with a small on-chip memory, the symbol decoding part consumes considerable DSP processing power. To improve the processing speed of this part, we propose an efficient symbol decoding structure where data are processed on an OFDM symbol basis and in-process data buffers are reused. As a result, during the entire symbol decoding process, all in-process data are stored on the fast on-chip memory without access to the slow external memory. To further improve the processing speed by reducing the number of load and store cycles required in the symbol decoding part, several function blocks are integrated into one function block. The validity of the proposed structure is confirmed by measurements of the execution cycle number and the bit error rate on an implemented T-DMB software baseband receiver.

Parallel Data Processing Based on EDMA to Save the Processing Power of a T-DMB Software Baseband Receiver Running on a Digital Signal Processor

Unlike symbol decoding and channel decoding, which perform a variety of computationally simple or complex algorithms in the T-DMB baseband receiver, time de-interleaving simply moves data between two buffers according to a specified rule. Nonetheless, such simple data movement consumes considerable processing power if the T-DMB baseband receiver is implemented in software running on a digital signal processor (DSP). In this work, we present a parallel data processing approach based on the enhanced direct memory access (EDMA) to perform time deinterleaving in a T-DMB software baseband receiver with the view of saving the DSP processing power. Results demonstrating the validity of the presented parallel data processing are presented in terms of the execution cycle count and bit error rate of an implemented T-DMB software baseband receiver.