Mooseop Kim

Design and implementation of Mobile Trusted Module for trusted mobile computing

This paper presents the design and implementation of a Mobile Trusted Module (MTM), which should satisfy small area and low-power condition. Unlike the general Trusted Platform Module (TPM) for PCs, the MTM, that is to be employed in mobile devices, has very stringent limitations with respect to available power, circuit area and so on. Therefore, MTM needs the spatially-optimized architecture and design method. We firstly introduce the design requirements for MTM and then implement a compact and power efficient MTM chip based-on the introduced requirements. The designed MTM can support all the necessary functions for trusted computing using 400K logic gates and consumes at most 10mA.

Efficient Hardware Architecture of SHA-256 Algorithm for Trusted Mobile Computing

We present a compact SHA-256 hardware architecture suitable for the Trusted Mobile Platform (TMP), which requires low-area and low-power characteristics. The built-in hardware engine to compute a hash algorithm in TMP is one of the most important circuit blocks and contributes the performance of the whole platform because it is used as key primitives supporting platform integrity and command authentication. Unlike personal computers, mobile platform have very stringent limitations with respect to available power, physical circuit area, and cost. Therefore, special architecture and design methods for a compact hash hardware module are required. Our SHA-256 hardware can compute 512-bit data block using 8,588 gates on a 0.25μm CMOS process. The highest operation frequency and throughput of the proposed architecture are 136MHz and 142Mbps, which satisfies processing requirement for the mobile application.

Low power implementation of SHA-1 algorithm for RFID system

In this paper, we implemented the low power and small area hardware of SHA-1 hash function for RFID tag. For small area design we optimized operation logics and for low power design we minimized data transitions of register memory. It is implemented with 10,641 gates at Samsung 0.25 mum CMOS technology and it needs 330 operation clocks for one hash function of 160-bit data. Its power consumption is 19.5 muW at 100 kHz operation clock

Low-cost Cryptographic Circuits for Authentication in Radio Frequency Identification Systems

We present a new architecture of Advanced Encryption Standard (AES) cryptographic circuit which can be used as cryptographic primitives supporting privacy and authentication for radio frequency identification (RFID). RFID is a technology to identify goods or person containing the tags. While it is a convenient way to track items, it also provides chances to track people and their activities through their belongings. For these reasons, privacy and authentication are a major concern with RFID system and many solutions have been proposed. M. Feldhofer, S. Dominikus, and J. Wolkerstorfer introduced the Interleaved Protocol which serves as a means of authenticating RFID tag to reader devices in M. Feldhofer et al., 2004. They designed very small AES hardware circuit as a cryptographic primitive. The proposed circuit requires about 1,000 clock cycles to encrypt a 128-bit block of data. In this contribution, we introduce a novel method to increase the operating speed of previous method for low-cost AES cryptographic circuits. Our low-cost AES cryptographic circuit can encrypt 128-bit data block within 870 clock cycles using less than 4000 gates on a 0.25 mum CMOS process

Efficient implementation of the keyed-hash message authentication code based on SHA-1 algorithm for mobile trusted computing

The Mobile Trusted Platform (MTP) is developed and promoted by the Trusted Computing Group (TCG), which is an industry standard body to enhance the security of the mobile computing environment. The dedicated SHA-1 and HMAC engine in Mobile Trusted Module (MTM) are one of the most important circuit blocks and contribute the performance of the whole platform because they are used as key primitives verifying platform code, integrity and command authentication. Unlike desktop computers, mobile devices have very stringent limitations with respect to available power, physical circuit area, and cost. Therefore special architecture and design methods for low power SHA-1 and HMAC circuit are required. In this paper, we present a compact and efficient hardware architecture of low power SHA-1 and HMAC design for MTM. Our SHA-1 hardware can compute 512-bit data block using about 8,200 gates and has a power consumption about 1.1 mA on a 0.25µm CMOS process. The implementation of HMAC using the SHA-1 circuit requires additional 8,100 gates and consumes about 2.58 mA on the same process.

An efficient data integrity scheme for preventing falsification of car black box

This paper propose an efficient scheme to enhance the security of vehicle black box. The proposed scheme can be used to prevent the falsification of black box data such as data forgery and modification. The proposed approach was tested using a commercial black box. The experimental results show that the proposed scheme is suitable for vehicle black box system to enhance the security of saved data.

Low power AES hardware architecture for radio frequency identification

We present a new architecture of Advanced Encryption Standard (AES) cryptographic hardware which can be used as cryptographic primitives supporting privacy and authentication for Radio Frequency Identification (RFID). RFID is a technology to identify goods or person containing the tags. While it is a convenient way to track items, it also provides chances to track people and their activities through their belongings. For these reasons, privacy and authentication are a major concern with RFID system and many solutions have been proposed. M. Feldhofer , S. Dominikus, and J. Wolkerstorfer introduced the Interleaved Protocol which serves as a means of authenticating RFID tag to reader devices in [14]. They designed very small and low power AES hardware as a cryptographic primitive. In this contribution, we introduce a novel method to increase the operating speed of previous method for low power AES cryptographic circuits. Our low power AES cryptographic hardware can encrypt 128-bit data block within 870 clock cycles using less than 4000 gates and has a power consumption about or less than 20 μW on a 0.25 μm CMOS process.

Power efficient hardware architecture of SHA-1 algorithm for trusted mobile computing

The Trusted Mobile Platform (TMP) is developed and promoted by the Trusted Computing Group (TCG), which is an industry standard body to enhance the security of the mobile computing environment. The built-in SHA-1 engine in TMP is one of the most important circuit blocks and contributes the performance of the whole platform because it is used as key primitives supporting platform integrity and command authentication. Mobile platforms have very stringent limitations with respect to available power, physical circuit area, and cost. Therefore special architecture and design methods for low power SHA-1 circuit are required. In this paper, we present a novel and efficient hard-ware architecture of low power SHA-1 design for TMP. Our low power SHA-1 hardware can compute 512-bit data block using less than 7,000 gates and has a power consumption about 1.1 mA on a 0.25µm CMOS process.

Design of Cryptographic Hardware Architecture for Mobile Computing

Abstract: This paper presents compact cryptographic hardware architecture suitable for the Mobile Trusted Module (MTM) that requires low-area and low-power characteristics. The built-in crypto-graphic engine in the MTM is one of the most important circuit blocks and contributes to the perform-ance of the whole platform because it is used as the key primitive supporting digital signature, platform integrity and command authentication. Unlike personal computers, mobile platforms have very strin-gent limitations with respect to available power, physical circuit area, and cost. Therefore special archi-tecture and design methods for a compact cryptographic hardware module are required. The proposed cryptographic hardware has a chip area of 38K gates for RSA and 12.4K gates for unified SHA-1 and SHA-256 respectively on a 0.25um CMOS process. The current consumption of the proposed crypto-graphic hardware consumes at most 3.96mA for RSA and 2.16mA for SHA computations under the 25MHz. Keywords:

System architecture for real-time face detection on analog video camera

This paper proposes a novel hardware architecture for real-time face detection, which is efficient and suitable for embedded systems. The proposed architecture is based on AdaBoost learning algorithm with Haar-like features and it aims to apply face detection to a low-cost FPGA that can be applied to a legacy analog video camera as a target platform. We propose an efficient method to calculate the integral image using the cumulative line sum. We also suggest an alternative method to avoid division, which requires many operations to calculate the standard deviation. A detailed structure of system elements for image scale, integral image generator, and pipelined classifier that purposed to optimize the efficiency between the processing speed and the hardware resources is presented. The performance of the proposed architecture is described in comparison with the detection results of OpenCV using the same input images. For verification of the actual face detection on analog cameras, we designed an emulation platform using a low-cost Spartan-3 FPGA and then experimented the proposed architecture. The experimental results show that the processing time for face detection on analog video camera is 42 frames per second, which is about 3 times faster than previous works for low-cost face detection.