Morihiro Kada

Thermal Stresses of Through Silicon Vias and Si Chips in Three Dimensional System in Package

Rbased on finite element method (FEM) was used to simulate the effects of voids formed inside Cu TSVs on the thermal conduction and mechanical stresses in the TSV structure. The thermal performance that was required in 3D SiP was estimated to ensure the reliability. Simulations for thermal stresses in the TSV structure in 3D SiP were carried out under thermal condition due to power ON/ OFF of device. In case that void was not present inside the TSV, the stresses in TSV were close to the hydrostatic pressure and the magnitude of the equivalent stress was lower than the yield stress of copper. Maximum principal stress of the Si chip in the TSV structure for the case without voids was lower than that of the bending strength of silicon. However, the level of the stresses in the Si chips should not be negligible for damages to Si chips. In case that void was present inside the TSV, stress concentration was occurred around the void in the TSV. The magnitude of the equivalent stress in the TSV was lower than the yield stress of copper. The magnitude of the maximum principal stress of the Si chip was lower than that of the bending strength of silicon. However, its level should not be negligible for damages to TSVs and Si chips. The stress on inner surfaces of Si chip was slightly reduced due to the presence of a void in the TSV. [DOI: 10.1115/1.4006515]

Stresses in 3D SiP with TSV under unsteady thermal loads

Recently, high density 3D packaging technology has been developed to reduce the size and improve the performance of semiconductor devices [1–10]. Through silicon vias (TSV) technique enabled downsizing of electronic devices and faster signal communication between semiconductor chips. The delay time of signal, which depended on circuit length, was reduced by direct communication with TSV as compared to the existing 2D structure by wire bonding method. Due to above advantages, 3D SiP (Three Dimensional System in Package) with TSV structure has been investigated in actively. However, much heat generation was induced by concentrated heat sources in 3D SiP. Strength of Si and Si wafer was evaluated by experimental methods and numerical simulations [11–13]. Several hundred MPa was reported at global area of Si and several GPa was reported at local area of Si. Large difference of strength was reported between at global area and at local area of Si. In cases of power ON/OFF of electronics devices and hot spot which was steep temperature increment in local area in devised, unsteady thermal loads should be considered as a potential for damages to Si chips, TSV and materials on 3D SiP.

Recent Research and Development Activities of Three-Dimensional Integration Technology

The second chapter describes the recent research and development history of three-dimensional (3D) integration technology. In this chapter we can see so many development activities in the word from 2013. It took 45 years from the beginning of TSV research and development for industry to begin high-volume manufacturing devices with this technology. Although some challenges related to reliability and cost remain.

Research and Development History of Three-Dimensional Integration Technology

The first chapter of the book introduces research and development history of three-dimensional (3D) integration technology. Concept of through-Si via (TSV) is old but the industrialization of 3D integration technology was leaded by 3D packaging technology first. 3D integration technology development using TSV have been conducted word wide since around 2000. This chapter describes the 3D technology development history from the beginning through 2012.

Dream Chip Project at ASET

Chapter 9 introduces the results of Japanese national research and development (R&D) initiative of 3D integration technology using through-silicon via (TSV) over the 5-year period from 2008 to 2012. Association of Super-Advanced Electronics Technologies (ASET) conducted the “Development on Functionally Innovative 3D-Integrated Circuit (Dream Chip) Technology Project,” and it was managed by the NEDO organization. The development subjects consisted of thermal management/chip-stacking technology, thin wafer technology, and 3D integration technology, ultrawide bus 3D-SiP, mixed signal (digital -analog) 3D, and heterogeneous 3D technology.

Combination between the nonlinear finite element analyses and the strain measurement using the digital image correlation for a new 3D SIC package

Numerical methods such as the finite element method (FEM) have been used to evaluate the reliability of electronic packages. However, it is difficult to assure the accuracy of numerical analyses of electronic packages, which require nonlinear analyses. In this study, we evaluated the thermal strain of a test chip for three-dimensional stacked integrated circuits (3D SIC) with both measurement and analyses. First, the distribution of thermal strain on the cross-section of the test chip was measured using the digital image correlation method (DICM). Then, the distribution of strain on the surface of a cut test chip was also analyzed by the FEM while considering the viscoelasticity of underfill (UF) resin measured with the stress relaxation test and the elastic-plasticity of components measured with nanoindentation testing. Based on the comparison between the DIC measurements and the FEM analyses, we improved the accuracy of the nonlinear finite element analyses.

Thermal Stress of Through Silicon Vias and Si Chips in 3D SiP

Thermal conduction and mechanical strength around TSV (Through Silicon Via) structures of 3D SiP (Three Dimensional System in Package) were discussed both cases of with and without void in TSV by using a large scale simulator based on FEM, ADVENTURECluster® for ensuring the reliability of 3D SiP. In the results, the thermal performance that was required in 3D SiP was estimated to ensure the reliability. Simulations for thermal stresses around TSV structure in 3D SiP under thermal cycle condition due to power ON/OFF were carried out. In case that void was not in TSV, stresses in TSV were close to hydrostatic pressure and the magnitude of the equivalent stress was lower than the yield stress of copper. However, the level of the stresses, especially in Si chips, should not be negligible in inducing damages to TSVs and Si single crystals. In case that void was in TSV, stress was concentrated around void in TSV and the magnitude of the equivalent stress was lower than the yield stress of copper. The level of stresses applied to Si chip was slightly reduced due to void in TSV. However, its level should not be negligible in inducing damages to TSVs and Si single crystals.Copyright