Morio Ikesaka

Architecture of highly parallel ap1000 computer

This paper describes the architectural features of the AP1000 message-passing computer. The architecture is designed to speed up barrier synchronization, data distribution and collection, broadcasting, and message handling. In recent message-passing computers, the most significant communication overhead is that associated with interrupt processing and message assembly/disassembly, because the adoption of new routing schemes has reduced the network latency. It is important for a fast message-passing computer to reduce not only network latency but also message handling latency. Although broadcasting, data distribution and collection, and barrier synchronization are necessary functions in many applications, these functions were slow in prior message-passing computers because each of these functions were simulated by many one-to-one communications. The AP1000 has three independent communication networks and message handling hardwares, fast barrier synchronization capabilities, and data distribution and collection hardware to speed up those functions.

Fast image generation of construcitve solid geometry using a cellular array processor

A general purpose Cellular Array Processor(CAP) with distributed frame buffers for fast parallel subimage generation has been developed. CAP consists of many processor elements called cells. A cell has video memory for subimage storage, a window controller to map each subimage to an area on the monitor screen, and communication devices, in addition to ordinary microcomputer components such as MPU, RAM, and ROM. Image data in a cell is directly displayed via the video bus. The mapping pattern and the position on the screen of subimages can be changed dynamically. Various hidden surface algorithms can be implemented in CAP using mapping patterns appropriate for the algorithm.Our goal is an efficient interactive visual solid modeler. We adopted a general CSG hidden surface algorithm that enables display of both Boundary representation and Constructive Solid Geometry. A technique for hidden surface removal of general CSG models, requiring less memory space for large models in many cases, has been proposed. This technique subdivides the model into submodels by dividing the CSG tree at union nodes. Imagse of each submodel are generated by a CSG or a z-buffer algorithm. If a submodel is just a primitive, it is processed by the z-buffer algorithm, otherwise by the CSG algorithm. Hidden surface removal between submodels is done by comparing the z values for each pixel which are saved in the z-buffer.

Cellular array processor CAP and applications

A description is given of a general-purpose, highly parallel, cellular array processor (CAP) featuring multiple-instruction-stream multiple-data-stream (MIMD) processing and image display. Processor elements can number in the several hundreds; the present system uses 256 processors. Each processor element consists of a general-purpose microprocessor, a memory, and a special VLSI chip that performs parallel-processing-specific functions such as processor communication and synchronization. The VLSI has two 2-Mbyte/s independent common interfaces for data broadcasting and six 15-Mbyte/s serial communication ports for local data communication. The chip can also process image data in real time for multiple processors. Use of the communication bus interfaces enables a variety of processor networks to be configured. One CAP application has been computer graphics, in which it uses ray tracing to generate quality images efficiently.<<ETX>>

A Highly Parallel Processor CAP

The aim of this study is to apply the unprecedented high-speed computing made possible by parallel processing to a wide range of problems such as computer graphics. A highly parallel cellular array processor, the CAP-256 has been developed in which 256 high-performance processors, called cells, are connected together. The CAP-256 includes a function by which a generated image is displayed in real-time, as well as a function to construct various kinds of [inter-processor] communication networks (topologies). A VLSI chip has been developed which integrates the communication and synchronization functions required for parallel processing, as well as the I/O function for the image. Using this VLSI chip, the cell was implemented in a compact form, and a small-sized high-performance parallel computer was implemented. To operate the cell, software called the cell OS (operating system) was developed. The software environment which has been implemented makes it possible to easily develop and efficiently execute application programs based on message communication. An image was generated using parallel ray-tracing which has three to four times higher performance than that of the general-purpose FACOM M-380 mainframe computer. The authors are also attempting to develop applications for CAD problems such as automatic wiring as well as scientific calculations. The versatility of the CAR-256 has been verified.