Moritoshi Yasunaga

Implementation of an Effective Hybrid GA for Large-Scale Traveling Salesman Problems

This correspondence describes a hybrid genetic algorithm (GA) to find high-quality solutions for the traveling salesman problem (TSP). The proposed method is based on a parallel implementation of a multipopulation steady-state GA involving local search heuristics. It uses a variant of the maximal preservative crossover and the double-bridge move mutation. An effective implementation of the Lin-Kernighan heuristic (LK) is incorporated into the method to compensate for the GAs lack of local search ability. The method is validated by comparing it with the LK-Helsgaun method (LKH), which is one of the most effective methods for the TSP. Experimental results with benchmarks having up to 316 228 cities show that the proposed method works more effectively and efficiently than LKH when solving large-scale problems. Finally, the method is used together with the implementation of the iterated LK to find a new best tour (as of June 2, 2003) for a 1 904 711-city TSP challenge

An Online EHW Pattern Recognition System Applied to Face Image Recognition

An evolvable hardware (EHW) architecture for high-speed pattern recognition has been proposed. For a complex face image recognition task, the system demonstrates (in simulation) an accuracy of 96.25% which is better than previously proposed EHW architectures. In contrast to previous approaches, this architecture is designed for online evolution. Incremental evolution and high level modules have been utilized in order to make the evolution feasible.

On-Chip Evolution Using a Soft Processor Core Applied to Image Recognition

To increase the flexibility of single-chip evolvable hardware systems, we explore possibilities of systems with the evolutionary algorithm implemented in software on an on-chip processor. This gives higher flexibility compared to implementing an evolutionary algorithm directly in hardware, since the parameters and behaviour of the algorithm can easily be changed, and complex operators are more feasible to implement. In this paper a Xilinx MicroBlaze soft core processor is used, and the system is implemented in a Xilinx FPGA. A suitable hardware architecture for image recognition has been proposed, and it is applied to a face recognition task. Data buses and higher level functions have been utilized in order to reduce the search space for the evolutionary algorithm. Experiments have been performed on the physical device, with software running in parallel with fitness computation in digital logic. Results show that the MicroBlaze system evolves at half the speed of a Pentium M system running at 17 times the FPGA clock frequency. The distinction of a certain face from others is performed at 94.9% accuracy. In addition, the possibilities for evolutionary adaptation over time are explored by introducing changes in the training set. The system shows ability to adapt to these changes

Genetic Algorithm-Based Methodology for Pattern Recognition Hardware

In this paper, we propose a new logic circuit design methodology for pattern recognition chips using the genetic algorithms. In the proposed design methodology, pattern data are transformed into the truth tables and the truth tables are generalized to adapt the unknown pattern data. The genetic algorithm is used to choose the generalization operators. The generalized, or evolved truth tables are then synthesized to logic circuits. Because of this data direct implementation approach, no floating point numerical circuits are required and the intrinsic parallelism in the data is embedded into the circuits. Consequently, high speed recognition systems can be realized with acceptable small circuit size. We have applied this methodology to the face image recognition and the sonar spectrum recognition tasks, and implemented them onto the developed FPGA-based reconfigurable pattern recognition board. The developed system demonstrates high recognition accuracy and much higher processing speed than the conventional approaches.

Online Evolution for a High-Speed Image Recognition System Implemented On a Virtex-II Pro FPGA

Online incremental evolution for a complex high-speed pattern recognition architecture has been implemented on a Xilinx Virtex-II Pro FPGA. The fitness evaluation module is entirely hardware-based in order to increase the speed of the circuit evaluation which uses a large training set (360 images/23040 bytes). The fitness evaluation time for 1000 generations consisting of 16 individuals is 623 ms, twice as fast as software fitness evaluation performed on a workstation running at a 30 times higher clock frequency. The rest of the genetic algorithm (GA) runs in software on a PowerPC 405 processor core on the FPGA. The total evolution time for 1000 generations is 1313 ms, equivalent to the total time used by the workstation. Resource utilization for the fitness evaluation module is 1393 slices (10%) of a XC2VP30 device.

A parallel hybrid genetic algorithm for multiple protein sequence alignment

This paper presents a parallel hybrid genetic algorithm (GA) for solving sum-of-pairs multiple protein sequence alignment. The method is based on a multiple population GENITOR-type GA and involves local search heuristics. It is then extended to parallel to exploit the benefit of a multiprocessor system. Benchmarks from the BAliBASE library are used to validate the method.

An online EHW pattern recognition system applied to sonar spectrum classification

An evolvable hardware (EHW) system for high-speed sonar return classification has been proposed. The system demonstrates an average accuracy of 91.4% on a sonar spectrum data set. This is better than a feed-forward neural network and previously proposed EHW architectures. Furthermore, this system is designed for online evolution. Incremental evolution, data buses and high level modules have been utilized in order to make the evolution of the 480 bit-input classifier feasible. The classification has been implemented for a Xilinx XC2VP30 FPGA with a resource utilization of 81% and a classification time of 0.5µs.

Evolvable sonar spectrum discrimination chip designed by genetic algorithm

DDI (data direct implementation) approach for pattern discrimination chips is proposed, and its specified design methodology is presented. In the design, pattern data are transformed to a truth table and the table is generalized to adapt the unknown pattern data. The generalization operator is chosen by using a genetic algorithm (GA). The generalized, or evolved truth table is then synthesized to logic circuits. This evolvable chip design methodology is realized by the high integration density of the current reconfigurable VLSIs. We have developed a prototype of the evolvable sonar discrimination chip. The prototype demonstrates higher discrimination accuracy and higher processing speed than conventional approaches. Furthermore, it shows high fault tolerance against stuck-gate faults, which is not achieved with the ordinary processor based hardware.

The design of segmental-transmission-line for high-speed digital signals using genetic algorithms

Ensuring the signal integrity even under pico-second switching-time in PCBs (printed circuit boards) as well as in VLSI chips is one of the most important goals in a PCB design. To achieve the goal, we propose a novel methodology of the PCB trace design in which the traces are regarded as segmental-transmission-lines of individual impedances. Also, the impedances are optimized by minimizing signal distortions due to multiple reflections in the transmission lines through genetic algorithms. Our design system shows excellent experimental results which achieves almost ideal signal wave forms without any signal distortion.

GP-based modeling method for time series prediction with parameter optimization and node alternation

A fast method of GP based model building for time series prediction is proposed. The method involves two newly-devised techniques. One is regarding determination of model parameters: only functional forms are inherited from their parents with genetic programming, but model parameters are not inherited. They are optimized by a backpropagation-like algorithm when a child (model) is newborn. The other is regarding mutation: nodes which require a different number of edges, can be transformed into different types of nodes through mutation. This operation is effective at accelerating complicated functions e.g. seismic ground motion. The method has been applied to a typical benchmark of time series and many real world problems.