Moustafa Mohamed

Reliability Modeling and Management of Nanophotonic On-Chip Networks

While transistor performance and energy efficiency have dramatically improved in recent years, electrical interconnect improvements has failed to keep pace. Recent advances in nanophotonic fabrication have made on-chip optics an attractive alternative. However, system integration challenges remain. In particular, the parameters of on-chip nanophotonic structures are sensitive to fabrication-induced process variation and run-time spatial thermal variation across the die. This work addresses the performance and reliability challenges that arise from this sensitivity to variation. The paper first presents a model predicting the system-level effects of thermal and process variation in nanophotonic networks. It then shows how to optimize many-core system performance and reliability by using run-time techniques to compensate for the thermal and process variation effects.

Iris: A hybrid nanophotonic network design for high-performance and low-power on-chip communication

On-chip communication, including short, often-multicast, latency-critical coherence and synchronization messages, and long, unicast, throughput-sensitive data transfers, limits the power efficiency and performance scalability of many-core chip-multiprocessor systems. This article analyzes on-chip communication challenges and studies the characteristics of existing electrical and emerging nanophotonic interconnect. Iris, a CMOS-compatible high-performance low-power nanophotonic on-chip network, is thus introduced. Iriss circuit-switched subnetwork supports throughput-sensitive data transfer. Iriss optical-antenna-array-based broadcast--multicast subnetwork optimizes latency-critical traffic and supports the path setup of circuit-switched communication. Overall, the proposed nanophotonic network design offers an on-chip communication backplane that is power efficient while demonstrating low latency and high throughput.

Global On-Chip Coordination at Light Speed

On-chip optical links are an efficient means of designing the communication backbone for massive multicore chips. Using nanophotonic technology lets designers develop a low-power, low-latency interconnection infrastructure for many-core chips.

Reliability-Aware Design Flow for Silicon Photonics On-Chip Interconnect

Intercore communication in many-core processors presently faces scalability issues similar to those that plagued intracity telecommunications in the 1960s. Optical communication promises to address these challenges now, as then, by providing low latency, high bandwidth, and low power communication. Silicon photonic devices presently are vulnerable to fabrication and temperature-induced variability. Our fabrication and measurement results indicate that such variations degrade interconnection performance and, in extreme cases, the interconnection may fail to function at all. In this paper, we propose a reliability-aware design flow to address variation-induced reliability issues. To mitigate effects of variations, limits of device design techniques are analyzed and requirements from architecture-level design are revealed. Based on this flow, a multilevel reliability management solution is proposed, which includes athermal coating at fabrication-level, voltage tuning at device-level, as well as channel hopping at architecture-level. Simulation results indicate that our solution can fully compensate variations thereby sustaining reliable on-chip optical communication with power efficiency.

Device modeling and system simulation of nanophotonic on-chip networks for reliability, power and performance

The nanophotonic network promises improved communications between cores in many-core systems. This paper discusses a novel modeling and simulation methodology. This infrastructure can compare performance, power consumption and reliability of nanophotonic network designs. Phenomenologically determined transfer-matrix device models are employed to characterize network performance under realistic multi-threaded applications, optical power transmission across the full wavelength-division multiplexing spectrum, and network reliability as affected by fabrication-induced process variation and run-time system thermal effects. Five recently proposed networks are analyzed to better elucidate advantages and limitations.

Power-efficient variation-aware photonic on-chip network management

Recent advances in nanophotonic technology have made nanophotonic interconnect an attractive on-chip communication solution for emerging many-core systems. However, fabrication-induced process variation and run-time system thermal effects directly affect nanophotonic device operation, and introduce serious challenges, e.g., signal power loss and crosstalk, to the power, performance and reliability of nanophotonic communication. This article first develops models to characterize nanophotonic process and thermal variation effects. Next, it presents a run-time management solution, an integration of inter-channel hopping, intra-channel wavelength tuning and variation-aware routing. Together, the proposed techniques can optimize the performance and reliability of nanophotonic communication with excellent power efficiency.

Modeling and analysis of micro-ring based silicon photonic interconnect for embedded systems

Recent advances in silicon photonic device and fabrication technologies make silicon photonic interconnect a promising communication fabric to address the inter-core and inter-die interconnect challenges for future embedded many-core processors. Informed design decisions in silicon photonic interconnection require optimization of performance, power efficiency, and reliability for different application scenarios. Optimizing these network and system metrics require understanding of silicon photonics device characteristics. However, existing design space exploration methodologies rely on time-consuming electromagnetic simulations or measurement of fabricated devices. In this paper, we introduce analytical models of devices, explore their design spaces, and apply them to different applications. The analytical models consist of parametrized transfer-matrices, with parameters categorized as fabrication-induced parameters and design parameters. Fabrication-induced parameters can be calibrated against measurements of fabricated devices to achieve high accuracy, whereas design parameters help in extrapolating the device characteristics. We develop and calibrate analytical models of widely used passive and doped micro-ring resonators. Three case studies of silicon photonic interconnects are discussed to represent different embedded applications and quantify the design trade-offs including performance requirements, power efficiency, and reliability constraints from the network system level.

Parameter extraction from fabricated silicon photonic devices

Three sets of devices were simulated, designed, and laid out for fabrication in the EuroPractice shuttle program and then measured in-house after fabrication. A combination of analytical and numerical modeling is used to extract the dispersion curves that define the effective index of refraction as a function of wavelength for three different classes of silicon photonic devices, namely, micro-ring resonators, racetrack resonators, and directional couplers. The results of this phenomenological study are made plausible by the linearity of the extracted dispersion curves with wavelength over the wavelength regime of interest (S and C bands) and the use of the determined effective indices to reconstruct the measured transmission as a function of wavelength curves in close agreement with experiment. The extracted effective indices can be used to place limits on the actual fabricated values of waveguide widths, thicknesses, radii of curvature, and coupling gaps.

Adiabatic Couplers for Linear Power Division

Adiabatic 3 dB couplers exhibit wide bandwidth and resistance to process and thermal variations. In this work, we investigate tradeoffs between sensitivity and overall length. The discussion includes plans for commercial fabrication.

Nanometric polymer coatings for silicon on insulator circuits

Applications of polymer post processing of silicon on insulator (SoI) devices are demonstrated. Polymer overlays on SoI nanophotonic circuits are used, on the one hand, to improve optical antenna transception for an any-one-to-all array and, on the other hand, a similar photodefinable coating is used to passively tune the dispersive characteristics of waveguides embedded in photonic crystals. Discussion is given to the polymer formulation. Coating that requires infiltration into voids with dimension 100 nm and less demands optimized wetting properties from the pre-cured polymer-in-solution. Atomic Force and Scanning Electron micrographs and Zygo interferometer image illustrate the quality of the post-photo-definition, cured coatings. Transmission measurements show a 10 dB improvement in the received signal level for a coated versus uncoated antenna pair radiating and receiving at 1550 nm. Wavelength dependent transmission measurements on waveguides in photonic crystals demonstrate that tuning can be affected in post processing performed after foundry fabrication. Careful formulation of the polymer for nano infiltration allows for tuning without increased attenuation.