Mrinmoy Bhattacharya

Some observations leading to multiplierless implementation of linear phase FIR filters

The paper explores alternatives for implementing a multiplierless implementation of linear-phase finite-impulse response (FIR) digital filters by converting coefficient values to minimum signed powers-of-two (MNSPT) or canonic signed digit (CSD) forms. Our observation is that if one is willing to accept some deviations in the given specifications, the required number of nonzero bits becomes quite low, making multiplierless implementation feasible. Alternatively, one may start with a filter that exceeds the given criteria, at the expense of a slightly increased filter order, and then quantize the coefficient values into the desired representation forms such that the given overall criteria are still met. In many cases, this results in an overall implementation where the total number of nonzero bits is significantly less than that obtained by using the initial design. A fairly exhaustive investigation suggests that less than three nonzero bits per multiplier are quite sufficient along with a reduction in number of arithmetic operations and an attendant increase in the rate of the data throughput.

Multiplierless implementation of recursive digital filters based on coefficient translation methods in low sensitivity structures

In the coefficient translation methods for reducing sensitivity in recursive filters the modified coefficients can be realized with multipliers of shorter wordlength i.e., by fewer number of bits. When these are implemented in minimum numbers of signed powers of two (MNSPT) form, we have a multiplierless implementation. These implementations are not associated with an increase in the order of the filter that involves an increase in complexity i.e., indirect overheads.

Some observations on multiplierless implementation of linear phase FIR filters

This paper investigates the case of multiplierless implementation of linear phase FIR filters by converting the multiplier coefficients to minimum signed powers-of-two (MNSPT) or canonic signed digit (CSD) forms. It was observed that if one is willing to accept some deviation from the given specifications, the required number of nonzero bits becomes quite low, making multiplierless implementation feasible. Alternatively, one can start with a filter that exceeds the given criteria that may involve an acceptable level of increase in the filter order, but with much lesser total number of nonzero bits than the initial design. Then, the coefficient values are quantized into the desired representation forms such that the given overall criteria are still met. Fairly exhaustive investigation suggests that less than three nonzero bits are quite sufficient, along with reduction in number of arithmetic operations with attendant increase in rate of data throughput.

Multiplierless implementation of bandpass and bandstop recursive digital filters

Multiplierless filters are natural extensions of the low-sensitivity structures. Some low-sensitivity transformations are investigated for converting a prototype lowpass filter into a bandpass or a bandstop filter. The resulting coefficient values, due to such transformations, become quite low compared with conventional structures. When the coefficient values are expressed in minimum signed powers of two (MNSPT) forms or canonic signed digit (CSD) forms, they require few shifts and adds and/or subtracts for implementation and a multiplierless realization can be obtained. Further, when we allow some marginally insignificant deviation in the specifications including the tolerances and the bandedges, the number of shifts and adds and/or subtracts per multiplier becomes quite small making this approach quite attractive. Alternatively, we can design the overall filter with marginally stricter tolerances than the desired specifications and meet the criteria after quantizing the coefficients.We investigate some low-sensitivity transformations converting a prototype lowpass filter into a bandpass or a bandstop filter. The resulting coefficient values become quite low compared with conventional structures. Hence, when the coefficient values are expressed in minimum signed powers of two (MNSPT) forms or canonic signed digit (CSD) forms, they require a few shifts and adds and/or subtracts for implementation and we obtain a multiplierless realization. Further, when we allow some marginally insignificant deviation in the specifications including the tolerances and the bandedges, the number of shifts and adds and/or subtracts per multiplier becomes quite small, making this approach quite attractive. Alternatively, we can design the overall filter with marginally stricter tolerances than the desired specifications and meet the criteria after quantizing the coefficients.

Multiplierless implementation of all-pole digital filters

For some low sensitivity structures, the coefficient values are quite small. These values after converting them to minimum signed powers-of-two (MNSPT) or canonic signed digit (CSD) forms can be implemented in a multiplierless manner, i.e., by using only a few bit shifts and adds and/or subtracts. In such cases, the number of nonzero bits required for coefficient representations become quite low. This paper proposes a structure that is very suitable for implementing all-pole digital filters. When accepting a marginal deviation from the given specifications, the required number of nonzero bits becomes very low, making the overall implementation attractive. Alternatively, one can start with a filter that slightly exceeds the given criteria without increasing the filter order. Then, the coefficient values are quantized into the desired representation forms such that the given overall criteria are still met.

Multiplierless realization of recursive digital filters using allpass structures

Under certain conditions, an odd-order lowpass or highpass recursive digital filter can be decomposed into the sum of two allpass filters with real coefficients. This decomposition has the attractive property that, for its implementation, there exist structures where both the number of delays and the number of multipliers are equal to the filter order, thereby making the overall implementation very efficient. The paper develops some allpass filter structures that combine this advantage with those of some low-sensitivity substitution and transformation blocks for replacing unit delay elements. These combinations enable one to generate multiplierless implementations for odd-order recursive digital filters and even-order bandpass and bandstop filters. Utilizing these structures, along with allowing some marginally insignificant deviations in the specifications, such as in the passband and stopband tolerances, the total number of nonzero bits for multiplier coefficients, i.e., those of shifts and adds and/or subtracts, becomes quite small, making this approach very attractive. Alternatively, the overall filter can be designed with marginally stricter tolerances than the desired specifications in such a manner that it meets the criteria after quantizing the filter coefficients.

Allpass structures for multiplierless realization of recursive digital filters

Under certain conditions an odd-order lowpass or highpass recursive digital filter can be decomposed into a sum of two allpass filters with real coefficients exhibiting a low passband sensitivity. This decomposition has the attractive property that there exist for its implementation structures where both the number of delays and the number of multipliers are equal to the filter order, thereby making the overall implementation very efficient. This paper develops some allpass structures that combine this property for generating multiplierless implementations for odd-order recursive digital filters. Utilizing these structures along with allowing some marginally insignificant deviations in the specifications such as in the passband and stopband tolerances, the total number of nonzero bits for multiplier coefficients, i.e., those of shifts and adds and/or subtracts, becomes quite small, making this approach very attractive. Alternatively, the overall filter can be designed with marginally stricter tolerances than the desired specifications in such a manner that it meets the criteria after quantizing the filter coefficients.

Multiplierless implementation of bandpass and bandstop IIR digital filters

Some low-sensitivity transformations are investigated, wherein a prototype lowpass filter is transformed into a bandpass (bandstop) filter with low-sensitivity using such transformation. The modified coefficients being quite small, they require few shifts and adds and/or subtracts for implementation when these are expressed in minimum signed powers of two (MNSPT) forms or canonic signed digit (CSD) forms, and we obtain a multiplierless realization. Allowing some marginally insignificant deviation in the specification including the tolerances and the bandedges, the number of shifts and adds and/or subtracts per multiplier becomes quite small to make this approach quite attractive. Alternatively, we can design the prototype lowpass filter with marginally stricter tolerances than the desired specifications. Our analysis confirms this approach to be a viable one for multiplierless realization of bandpass and bandstop filters.

Recursive structure for linear filtering using number theoretic transform

Where speed of computation, i.e. data throughput, is not a constraint, it is feasible to implement digital signal processing algorithms in a bit serial fashion. One could employ look-up tables for realizing the difference equation eliminating the generally costly multiplier stage. We get a low power implementation as the power dissipation is quite low due to bit serial implementation and lower throughput rate of data. It is possible to implement filtering using number theoretic transform (NTT) for certain choices of modulus in structure that is completely different from the typical FFT structure, although the lengths considered are square numbers and quite composite. To mention a few advantages, there is no data index management in intermediate stages or twiddle factor multiplications and complex multiplications unlike typical FFT structures, low multiplication per point compared to FIR filtering, and low power consumption, while some marginal complexity due to modulo arithmetic remains.

Multiplierless implementation of recursive digital filters using a class of low sensitivity structures

One of the method of reducing coefficient sensitivity is that of coefficient translation. The structure is altered in such a way that the sensitivity with respect to the modified coefficients is reduced to a great extent compared to that with respect to the original coefficients. In low sensitivity structures the modified coefficients can be realized with multipliers of shorter wordlength i.e., in fewer number bits. When these are implemented in minimum numbers of signed powers of two (MNSPT) form, we have a multiplierless implementation These implementations are not associated with increase in the order of the filter that involves more number of shift registers, data paths, control circuits, etc., and hence, an increase in complexity i.e. indirect overheads.