Mu-Hsuan Chan

Development of thermal compression bonding with Non Conductive Paste for 3DIC fine pitch copper pillar bump interconnections

High density interconnection is a key technology to realize the miniaturization trend in Integrated Circuit (IC) industry, and to reduce power consumption for next generation mobile devices. In advanced three-dimensional (3D) package, fine pitch pillar bump is deployed not only to fulfill ever-growing I/O density requirement, but also provides better electrical performance than that of traditionally solder bump [1]. Meanwhile, to maximize die area utilization, die sizes of top and bottom die are generally kept as close as possible, leaving stringent spacing for underfilling, and makes fillet width control and dispense space two great challenges for capillary underfill (CUF). In this paper, test vehicle of fine pitch micro-bump interconnection was achieved by thermal compression bonding (TCB) with Non-Conductive Paste (NCP). This paper addresses development of TCB process with NCP material by different TCB condition and NCP properties to show the correlation between TCB process parameter and NCP material. In order to achieve spherical bump shape, NCP gel time was studied in different bump melting time. Fillet width was studied to control the exceeding area around chip. Void was also studied for TCB parameter adjusting. Finally, reliability test was tested for NCP properties discussion.

Thermal cycling effect on intermetallic formation with various surface finish of micro bump interconnect for 3D package

Micro bump interconnect with through-silicon via (TSV) is one of the critical issues for realizing three dimensional (3D) packages. This enabling technology provides more I/O in shrunken die area, and hence high density interconnection. Electroless Ni immersion Au (ENIG), electroless Ni electroless Pd immersion Au (ENEPIG), and plating Tin are commonly used surface finish for Cu pad in lead-free package. However, the majority of studies are focusing on Controlled Collapse Chip Connection (C4) solder. Intermetallic compounds (IMC) formation is a result of interaction between the solder tip, barrier layer, Cu pillar form the top die and micro pad finish from the interposer. As a result, microstructure made with different pad finish will major impact to solder reliability. In this study, three types of pad finish including ENIG, ENEPIG, and plating Tin were chosen to evaluate intermetallic formation during thermal cycling test. In addition, presence of Ni was also discussed to understand IMC formation in this microstructure. Multi reflow (at time zero, 1×, 3×) and thermal cycling test were performed for this evaluation. Metallurgy and growth kinetics of IMC were compared at different thermal cycling. The results show that SnAg bump with ENEPIG pad finish have more Cu consumption than ENIG after pre-con. ENEPIG pad finish exhibits crack formed between (Ni, Cu)6Sn5 and P-rich layer. The detailed influence of Ni with various pad finish on the growth kinetics of IMC formation was investigated and discussed.

A study on the 3DIC interconnection using thermal compression bond with non conductive paste process

Three dimensional (3D) stacking technology has been purposed to meet miniaturization trend, high performance, and multi-function electronic products. Chip stacking with through silicon via (TSV) and high density lead free interconnection are believed to realize 3D stacking package. Due to the narrow dispensing request for multi-chip connection, non-conductive paste (NCP) is one of the solutions to replace capillary underfill. Nevertheless, voidless control and wettability are two critical challenges for large dies size flip chip ball grid array (FCBGA) 3D package. In this paper, fine pitch u-bump for large die size 3D stacking using thermal compression bonding (TCB) with NCP is demonstrated. In order to achieve voidless, bonding parameter was studies in different pre-heat time. The effect of bonding conditions such as force, temperature, and time on wettability has been performed. The results showed that longer pre-heat time could accomplish voidless. The u-bump wettability exhibited relationship between TCB parameters and characteristics of NCP. Finally, reliability test was tested for NCP properties discussion.

Effects of cleaning process on the reliability of ultra-fine gap for 3D package

Fine pitch interconnection is a key stream to accommodate increased I/O applications. This enabling technology provides more I/O in shrunken die area, and hence high density interconnection. However, the majority of studies are focusing on the solder material and failure mode by using various intermetallic compounds (IMC) formation. In order to improve the reliability of the mirco-interconnects, it is indispensable to remove flux residues in the center of the package as clean as possible through washing process to avoid the delamiantions along the interfaces between the u-joint and the underfill. Spin cleaning replace conventional water jet to challenge ultra-fine gap for 3D package. As a result, cleaning procedures with different chemical solvent will major impact to cleaning situation. Several DOEs have been constructed for solvent to increase BGA reliability by optimizing cleaning process. A comparison of flux cleaning process technologies for chip and wafer level interconnection were be discussed. This paper shows methods and comparison of the conveyer, spin clean, water jet for chip level, and spin cleaning for wafer level. In addition, multi reflow (at time zero, 1×, 3×) and thermal cycling test were performed for underfill delamiantion. The detailed influence of u-joint with various bump density on the hydrodynamics was investigated and discussed.

Effective 3DIC chip module warpage with UF design by analytical method

Three dimensional (3D) stacking technologies have been popular among in high level package that can meet miniaturization trend, high performance, and multi-function electronic products. The interposer where the chips are stacked on is an electrical interface routing between one socket or connection to another. Underfill (UF) material is required to fill in the gap between chip and interposer for protecting u-bumps interconnection. Nevertheless, higher coefficient of thermal expansion (CTE) of UF material to lead chip module of 3DIC package warping, so that to cause bridge or non-wet issue during chip module on substrate process. The purpose of this paper is to study the root cause which influences the warpage of 3D stacked chip module. Firstly, the key factors of underfill material properties were selected by experimental study. Furthermore, The JMP Taguchi Orthogonal Table (L9:3^4) & FEM simulation were implemented to get maximize desirability of UF material property in warpage result of chip module. Finally it is concluded that the final warpage results can be successfully predicted to avoid bridge or non-wet issue during chip module on substrate process.

Underfill adhesion enhancement via optimization of plasma treatment for 3DIC

For the advanced 3DIC packages with features as large die dimension and fine bump pitch, plasma was difficult to penetrate into the center of package. Plasma power, treating time, and gas flow rate were evaluated in this study to enhance the penetration ability of oxygen radical. Contact angle measurement was taken to judge the treatment effect. For the package with die size beyond 25 × 25 mm, contact angle on the organic substrate beneath die could be decreased to 40 degree via recipe optimizing. For high I/O count package with 40 um stand-off height and 45μm pitch, decrease of contact angle at internal surface was also achieved. Shear test presented that the adhesion was enhanced via optimized plasma treatment.

High thermal conductivity underfill study for fine pitch Cu pillar bump

Along with the die size of device become more and more small, fine pitch, fine gap and multi-stacking are the market mainstream which applied for high performance system in advance technology, su ch as 3D IC. Th erefore, h eat dissipation is must process for this kind of electronic device to avoid internal heating form device during operate. Un derfill (UF) is an important process in 3D stackin g flip chip package that major function is reducing stress from coefficient of thermal expansion (CTE) mismatch, also can isolate bump and protect it. In this study, two kinds of fillers are evaluated on the heat dissipation which one is Silica and the other is Alumina. In order to clarify the performance of the test results, adhesion test was performed by pudding model on the silicon nitride. In addition, UF filing and flowing capability was determined by scanning acoustic tomography (SAT). Thermometer was used to analysis heat dissipation for comparing the effect of different UF filler material.

Reliability of thermal compression bond combine with non conductive paste process in fine pitch micro-bumps soldering

In order to meet the miniaturization trend and to reduce the power consumption for next generation devices, three-dimensional (3D) stacking is believed to be one of the technologies that can meet these requirements. In advanced 3D stacking technologies, one of the important steps is to develop and assembly fine pitch and high density microbumps. However, while the stacking chip size of top die and bottom die are similar, there is not enough space to dispense underfill, so it is a challenge for conventional underfill (CUF). In this paper, thermal compression bond (TCB) combine with non conductive paste (NCP) were studied. Adhesion between NCP and SiN, adhesion between NCP and PI, simulation of stress between bumps and chips were carried out and discussed. Finally, reliability test results were also reported in this paper.