Mu-Shui Zhang

An Efficient Algebraic Method for the Passivity Enforcement of Macromodels

In this paper, an efficient algebraic method for the passivity enforcement of macromodels is presented. The method is based on quadratic programming with equality constraint. The differences between equality constraint and conventional inequality constraint are discussed. Compared with the general quadratic programming-based method, where the passivity violations are compensated via numerical optimization, the presented method is based on the solution of sparse linear equations. With the special sparse structure of macromodels, the passivity compensation is equivalent to the solution of some small size linear equations. This gives large savings for CPU time and memory requirement. Several examples show that the presented method yields accurate passive macromodels in a limited simulation time.

Power Noise Suppression Using Power-and-Ground Via Pairs in Multilayered Printed Circuit Boards

In this paper, an efficient power noise suppression method using power-and-ground (PG) via pair array in multilayered printed circuit boards (PCBs) is proposed. The power noise suppression performance is doubled by using both power and ground vias compared with the ground via array. The stopband bandwidth of the PG via pair array is derived. The evolvement from mushroom electromagnetic bandgap (EBG) structure to PG via pair array is demonstrated. The proposed method has overcome many shortcomings of the mushroom EBG structures. It is shown that the PG via pair array has excellent power noise suppression, signal integrity (SI), and electromagnetic compatibility (EMC) performance. It is a comprehensive power noise suppression scheme.

An Efficient SPICE-Compatible Cavity Resonant Model for Microstrip Lines

A SPICE-compatible cavity resonant transmission line (CTL) model for a single-ended microstrip line is first presented by reducing 2-D cavity resonator to 1-D cavity resonator. This model has low efficiency since it consists of infinite higher-order components included inductors, capacitors, resistors, and ideal transformers. A modified CTL model is developed by using a fast algorithm to improve the simulation efficiency, which results in an accurate SPICE model in finite elements. Because the improved cavity resonant model uses higher-order (a little more complicated) elements in finite components, it has high efficiency in the time and frequency domain simulation. The model accuracy and simulation efficiency are validated by comparison with multiconductor transmission line and matrix rational approximation modeled methods.

Pin Assignment Optimization for Large-Scale High-Pin-Count BGA Packages Using Genetic Algorithm

In this paper, a power/ground (P/G) pin optimization method using genetic algorithm (GA) is proposed for large-scale high-pin-count ball grid array (BGA) packages. Two objective functions are derived for signal integrity and power integrity, respectively. A general optimization flow is presented, where the basic concepts of GA optimization are introduced and some important considerations for package design are demonstrated. A customized GA flow and two accelerating strategies are developed to improve the efficiency of the optimization procedure. Using GA optimization, the P/G pin assignment of a 40 × 40 BGA package with blocks of core, inputs/outputs and differential pairs can be generated in a few tens of minutes automatically.

Modeling, Analysis, and Design for Noise Suppression Using Embedded Planar Capacitors in Multilayered Printed Circuit Boards

In this paper, an accurate and fast method is presented for the modeling, analysis, and design of the power noise suppression using embedded planar capacitors in high-speed multilayered printed circuit boards (PCBs). Two main contributions of this paper are: 1) an ideal AC short circuit model is proposed to simplify the stopband analysis and a physics-based formula is derived for accurate stopband estimation and 2) a physics-based equivalent circuit modeling method is introduced for the fast estimation of noise suppression level in complicated multilayered structures. The results are verified by simulation and measurement. Our method changes the analysis of complicated multiple plane pairs into single plane pair, which can greatly simplify the design process of embedded planar capacitors in complicated multilayered PCBs.

New Power Distribution Network Design Method for Digital Systems Using Time-Domain Transient Impedance

In this paper, a power delivery network (PDN) design method using new time-domain transient impedance is proposed for high-speed digital systems designs, with verification by examples and simulations. This method is based on a new triangular pulse representation of a step transient current demand. Compared with the frequency-domain target impedance method, the proposed method results in a much smaller decoupling network, as it only consider the basic power delivery function of the PDN and the time-domain transient impedance has flat impedance response. The proposed time-domain method provides a good preliminary design for large complicated PDN using lumped model analysis.

A New Systematic Method for the Modeling, Analysis, and Design of High-Speed Power-Delivery Networks by Using Distributed Port

In this paper, a new concept of distributed port is proposed, and a systematic method for the modeling, analysis, and design of the high-speed power delivery network (PDN) is developed. The distributed port uses multiple lumped ports dispersed uniformly in the power-delivery networks to capture the distributed characteristics of the large and irregular power-delivery structures. This concept provides a feasible scheme for the accurate analysis of the whole or any part of a power-delivery network. The modeling methods and modeled results are discussed in depth. The applications of the distributed port in the PDN design, systematic PDN modeling, and package/connector performance evaluation and optimization are discussed in detail. The validity of the distributed port is demonstrated by numerical examples and verified by simulations and extractions.

Static Template for Fast Power/Ground Pin Assignment of Large-Scale BGA Packages Using Genetic Algorithm

In this paper, a fast power/ground (P/G) pin assignment method for large-scale high-pin-count ball grid array (BGA) packages using static template is proposed. The static template is generated using genetic algorithm. An algorithm is developed to remove the boundary problem of the static template so that its copies can be directly merged into a large-scale BGA package. The selection of the size of static template is demonstrated. A visual demonstration method is presented to better evaluate the quality of the assignment of signal and P/G pins by human eyes. Using static template method, the pin assignment of a 50 × 50 BGA package with blocks of core, I/Os and differential pairs can be generated in a few tens of seconds automatically.

Accurate Delay Extraction of Serpentine Lines for Next-Generation High-Density DRAMs

As trace dimension reduces to 2 mil or smaller in next-generation high-density DRAMs, length matching design using serpentine lines could result in timing error larger than 50%. Significant coupling in parallel segments of serpentine lines could greatly affect the propagated speed of digital signals. In this paper, accurate delay extraction for serpentine lines is proposed. Formulas for accurate delay extraction are presented, and guidelines for minimized crosstalk are developed. Two main contributions of this paper are: 1) delay of serpentine lines is first accurately extracted by mathematical formulas and 2) an interesting undistorted transmission mode of serpentine lines is first analyzed. Electromagnetic simulated results show that our method yields accurate delay with error smaller than 10%, while traditional delay estimation could introduce error larger than 130%.

Pin Assignment Optimization for Large-Scale High-Pin-Count BGA Packages Using Simulated Annealing

In this paper, a power/ground (P/G) pin assignment method using simulated annealing (SA) for large-scale high-pin-count ball-grid-array (BGA) packages is proposed. Two objective functions describing the power integrity (PI) and signal integrity (SI) of the pinout are introduced. The SA algorithm is customized to meet the needs of the pin assignment problem. Accelerating strategies are introduced, and some special considerations for customized SA optimization are discussed. The SA method can generate large-scale P/G pinout with any power-ground-signal pin ratios (P0/G0/S0) in a few minutes. Large-scale BGA packages with more than 2000 pin numbers including the I/O, core, and different-pair blocks can be generated by the proposed SA method quickly, with a similar PI and SI performance compared to the products from Xilinx and Altera.