Muataz H. Salih

Enhance implementation of embedded robot auto-navigation system using FPGA for better performance

Nowadays, Auto-navigation robots are cutting-edge and widely used and investigated by robotics experts. An autonomous robot can function and complete every task without any human guidance. Since it functions without human intervention, therefore obstacles detection and localization are significant and need to figure out. First, how the robot obstacle detection? Second, how to control auto-navigation robot localization accuracy and stability motion of the robot? Both of conditions would significantly affect performance and accuracy of robot to detect and reach destination. Therefore, we needed to figure out few solutions to solve these problems before create an auto-navigation system. Initially, testing and using suitable detection sensors and design suitable algorithm for sensor to detect obstacles. Then, Global Positioning System (GPS) would be used to calculate based upon information from GPS receiver to mapping the shortest path for robot to reach destination. Lastly, timing of the robot will generate by using 50MHz default frequency of DE0-Nano to control motors and direction of the wheels. In addition, using DE0-Nano board the design operating frequency can reach maximum 1GHz. Furthermore, the potential resources of Quartus II version 14.1 are utilized to implement supported modules of auto-navigation robot stages. The design had been carried out on Altera Cyclone IV FPGA. The autonavigation robots were provided higher flexibility and could help people do to something which will develop into life-threatening. So that, its rapidly enlarging on industry floor.

Embedded Concurrent Computing Architecture using FPGA

Simultaneous multithreading by use of embedded parallel systolic filters is a novel technological approach to achieve multiprocessing. It is important for the designers to ensure that FPGA chips that are fully operational. There is great emphasis on the design area, performance, challenges and opportunities posed by multi-tasking as a result of the huge number of inputs and outputs required by the design. The Embedded Concurrent Computing Architecture proposed is implemented on a FPGA chip. There are expected speedups in the implementation based on the results shown in this proposal. Synthesis has been used in gathering of the results with implementation being achieved by use of low complexities in the FPGA usage and frequency. The efficiency of the new model is over 75% with the performance of the design is secured for a tolerance of 2 m for 25 m range. The Particle filter tolerance is less than 1m with an operating frequency of 212 MHz or thereabouts.

Enhance implementation of flying robot auto-navigation system on FPGA for better performance

The complexity to autonomous-navigate a flying robot is much higher compared with a ground-based robot. During autonomous-navigation, the flying robot should have the intelligent to fly from current location toward the desired location. Therefore, the system must address three problems facing by the flying robot. First, where am I? Its the perceive level of the flying robot to sense the environment. Second, where am I going? The flying robot must possess the knowledge on the areas located. With all of the information, the flying robot is capable to address the third questions, figuring how to go there. The main intention of this paper is to devote the autonomous navigation system on flying robot. Significant parameter on the system like in term of frequency, accuracy, etc. will be improve or enhances in this paper. Sensors such as Global Positioning System (GPS), ultrasonic range (US) sensor, etc. was implemented on the flying robot. This sensor was operated as the sensing unit in the flying robot to provide the physical knowledge for the surrounding environment. Then the flying robot would be able to generate a path toward the desired location. To flying safely during task, flying robot has to continually acquire the environment knowledge time by time. Besides, its also important to maintain the stability of the flying robot when performing the entire task. All of the module would combine as final module name autonomous navigation system. The system would make the decision based-on the stage of the task. All of the module would implement on FPGA using VHDL and process with DE0-Nano as the on-board computer. The system was successfully implemented on the flying robot. Its still under progress to perform the outdoor autonomous navigation without human supervised. The objective to devote the system is under progress.

Design and implementation of embedded DAQ using spatial parallelism on FPGA for better throughput

Data acquisition (DAQ) is the process of acquire analog signals from different types of sources and further process the acquired signals through personal computer (PC) in digital form. Compared to traditional measurement system, PC-based DAQ system provides a more flexible and cost-effective measurement solution to the industry and utilizes the efficiency, processing power and connectivity capabilities of industry-standard computers. Nowadays, the electronic based industry is becoming more advanced with the recent technologies used in implementing their design and product. Therefore, the requirement of DAQ system has to be increased in terms of flexibility, accuracy and reliability. In the past development of such DAQ systems have been seen that are not competency in terms of data accuracy and system throughput. On the other hand, the main processing unit which is to gather, process and generate the output data is work sequentially which might be results in lack of efficiency and flexibility. In this paper, a new embedded DAQ unit using spatial parallelism on Field Programmable Gate Array (FPGA) which produced high accuracy and throughput was designed and implemented using DE0-Nano FPGA board. Up to 7 input channels will be processed concurrently through spatial parallelism and focused on its data accuracy and system throughput. Furthermore, in order to achieve a higher processing speed and increase the data accuracy, the overall system design reached 1GHz operating frequency.

Design and implement active embedded robot tracking system using FPGA for better performance

Active robot tracking system is one kind of utilization of tracking system on a mobile robot and widely used in many aspect such as security or military. With the widespread of application of robot tracking system, it is necessary that the development of this robot tracking system that facilitate future enhancement. However, problem of detecting the object, planning path and avoiding obstacles during tracking the object is an important issue in mobile robot tracking system. Plentiful of sensors had been used to solve these problems and one of the FPGA platforms is chosen in this project. Active robot tracking system can detect a moving object, set it as target and follow the trail of target. In this project, two infrared distance sensor are chosen to be the tracking sensor to detect any moving object while an ultrasonic sensor as the obstacle avoidance sensor. To well-know the FPGA platform used, some understanding on it is done. Then, some testing on characteristic of sensors and on robot stability carried out to master those sensor and robot well. Next, those sensor and robot platform interfaced with the DE0 Nano board. After that, the coding VHDL used to overcome design challenges. After all, the design will try on the robot platform and tuning up. At the end of result, the tracking system found that is flexible used in any two wheeled robot, respond faster, modified easily and high frequency.

Modelling and Simulation of Rectangular Bundle of Single-Walled Carbon Nanotubes for Antenna Applications

This paper aims to present an effective electromagnetic (EM) modelling approach for rectangular bundle of single-walled carbon nanotubes (RB-SWCNTs), based on the electrical conductivity, relative complex permittivity and linear distribution impedance by applying General Ohm’s law for this bundle. The equivalent single conductor material (ESCM) model for personification the RB-SWCNTs is present in this paper. The main target of this modeling approach is to estimate and investigate the EM properties of RB-SWCNTs using common EM engineering tool solver CST (MWS). For this purpose, the RB-SWCNTs and ESCM dipole antennas will be designed and implemented using CST (MWS). The equivalent conductivity model, relative complex permittivity and other parameters of the RB-SWCNTs will be derived in this paper and considered as an equivalent material parameters for the ESCM. This modeling technique is expected to provide new avenues for designing different antenna structures.

Design and implementation computing unit for laser jamming system using spatial parallelism on FPGA

When a system completes processing a number of functions in a given amount of time, the condition that drives it to do so is called a real-time system. The processing platforms of projective missile system face two major problems: structure complexity and high cost. The complexity in the system structure is a result for multi reasons such as the mechanism used within the system to perform the system functionality and this can cause delay in the data processing which occurs because of various factors, including the architecture of the processing unit, the way the signals in the system modules are synchronized, and the computational power of the unit. In order to reduce the system complexity as well as the system cost, we proposed in this paper applying the spatial parallelism mechanism and a concurrent structure over our embedded system. We used the FPGA platform (NEEK board) to be the implementation environment for this system which resulted in enriching our proposed system with core features such as the low cost as well as decreasing the system complexity since the concurrent structure is used within this system. The spatial parallelism can provide the ability for duplicating the tasks which can be processed via specific modules. We covered in this system signals ranging from 1 Hz to 200 MHz. To avoid the limitation of the master clock of the Nios II Embedded Evaluation Kit, we manipulate the Phase Locked Loop to enable the system from covering wide spectrum of signals. Our laser projective frequency jamming system has the ability to process multiple frequencies per time. The implementation has achieved acceptable throughput and lower complexity (small size (2604)) logic elements in terms of FPGA resource usage and high operating frequency (200 MHz). In addition, the structural design methodology also allows scalability of the embedded concurrent computing architecture as the entire system grows.

A low-complexity sphere detection technique for orthogonal frequency division multiplexing systems in selective fading channels

This paper presents a low-complexity detection scheme, which consists of a lattice sphere decoder (LSD), for Orthogonal Frequency Division Multiplexing (OFDM) systems. The inter-carrier interference (ICI) resulting from selective fading channel destroys the orthogonality of the OFDM signal and poses a significant limitation on wireless OFDM systems. The aim of this paper is to propose an efficient detection technique in order to provide reliable communications using OFDM in selective fading channels. The proposed detection technique combines the new LSD with two regularization methods. Theoretical analysis and simulation results show that the proposed detection scheme substantially improves the symbol error rate (SER) performance of OFDM systems. Moreover, its complexity is 22 times lower than that reported in a previous work, and 51 times lower than the complexity of the original sphere decoding (SD) technique.

FPGA based embedded homogenous and hetrogenous multi-processor SoC design: A review

The huge and fast development in all our life aspects motivated the system designers to increase system performance and in the same time decreasing the cost and power consumption. FPGAs based embedded systems can provide the equilibrium between many critical concepts like, performance, rapid time to market, and flexibility, so they have become the preferred source of computation in many critical embedded systems. The wide variety of needed tasks and new life facilities pushed towards highly reactive and multi-functional systems. This was the main reason that assists replacing the simple processing units with heterogeneous multi-processor units. The main advantage of using heterogeneous multi-processing units in field programmable gate array is to perform specific functions in almost real-time respond and the ability to reconfigure these units and decreasing the time required for re-mapping the application into the new architecture when the architecture changes. In the same time heterogeneity has its own problems also, like synchronization, communication between different computational units and also resources management. This paper will review a proposed heterogeneous multi-processor platform, the way to handle the synchronization between processors, the way in which these processors are communicate with each other or exchange information between them when needed and how a sequence of tasks can be scheduled to be processed.