Muhammad E. S. Elrabaa

Advanced low-power digital circuit techniques

List of Figures. List of Tables. Preface. 1. Low-Power VLSI Design. 2. Low-Power High-Performance Adders. 3. Low-Power High-Performance Multipliers. 4. Low-Power Register File. 5. Low-Power Embedded BiCMOS/ECL SRAMs. 6. BiCMOS on-Chip Drivers. 7. Inter-Chip Low-Voltage Swing Transceivers. References. Index.

An Efficient Network-on-Chip Architecture Based on the Fat-Tree (FT) Topology

A novel approach for an efficient network-on-chip using a modified Fat Tree is presented. Contention is eliminated and latency is reduced through an improved topology and router architecture. The adopted topology increases performance without a substantial increase in the routing cost. This is achieved by using an improved buffer-less, paremeterizable router architecture. The proposed router architecture is simple to implement yet can achieve the required packet collision avoidance. Simulation results that show the level of performance achieved by both the topology and the router architecture are presented. A throughput of more than 90% is achieved way above the 40-50% usually seen in other networks on chips.

Novel low-voltage low-power full-swing BiCMOS circuits

A novel BiCMOS full-swing circuit technique with superior performance over CMOS down to 1.5 V is proposed. A conventional noncomplementary BiCMOS process is used. The proposed pull-up configuration is based on a capacitively coupled feedback circuit. Several pull-down options were examined and compared, and the results are reported. Several cells were implemented using the novel circuit technique; simple buffers, logic gates, and master-slave latches. Their performance, regarding speed, area, and power, was compared to that of CMOS for different technologies and supply voltages. Both device and circuit simulations were used. A design procedure for the feedback circuit and the effects of scaling on that procedure were studied and reported. >

Optimization of digital BiCMOS circuits, an overview

An overview of the optimization of buffer chains and multilevel logic in a BiCMOS environment, including scaling effects, is presented. The BiCMOS speed-up contours are reviewed. The use of these contours and analytical delay expressions in the design and optimization of BiCMOS buffer chains is also reviewed. The performance differences between different types of multi-stage mixed CMOS/BiCMOS buffers are summarized. Different BiCMOS current-mode logic (CML) circuits, such as the multi-emitter BiCMOS CML circuits, are considered. The performance advantages of using such circuits in implementing multilevel logic are summarized.<<ETX>>

A new static differential CMOS logic with superior low power performance

A new differential static CMOS logic (DSCL) family is devised. The new circuit is fully static, making it simple to design. The circuit topology of the DSCL and its operation is explained. Delay optimization of the new circuits was performed. It showed the fully static behavior of these circuits. Their performance in terms of delay, power, and area is compared to that of conventional static differential logic and dynamic differential logic. Spice simulations using a 0.18 μm technology with a power supply of 1.8 V was utilized to evaluate the performance of the three circuits. Two different sets of simulations were carried out; one with equal input capacitances of all circuits and another with equal circuit delays. For each design, all circuits were optimized for minimum delay. It is shown that at equal input capacitance, the DSCL achieved 40% less delay than the DCVSL at one third the power. Also, at equal delay, the DSCL achieved 20% of the power dissipation of the DCVSL and 78% of the DDCVSL making it the most energy-efficient among the three circuits.

Design and optimization of buffer chains and logic circuits in a BiCMOS environment

The design and optimization of BiCMOS buffer chains and multi level logic circuits are reported. BiCMOS speedup contours are introduced and analytical expressions for the delay are obtained. The speedup contours and the delay expressions were used in the design and optimization of BiCMOS buffer chains. Also, general design guidelines, which can be easily automated, for circuit design in a BiCMOS environment are given. Designing multistage mixed CMOS/BiCMOS buffers, BiCMOS complex logic gates, and multi level CML (current mode logic) gates is also studied. >

IMPROVED MODIFIED FAT-TREE TOPOLOGY NETWORK-ON-CHIP

C-based cycle-accurate simulations are used to evaluate the performance of a Network-on-Chip (NoC) based on an improved version of the modified Fat Tree topology. The modification simplifies routing further and guarantee orderly reception of packets without any loss of performance. Several traffic models have been used in these simulations; Bursty and non-bursty traffic with uniformly-distributed destination addresses and non-uniformly-distributed destination addresses. A simple new traffic model has been developed for generating non-uniformly-distributed destination addresses. This model is general enough to be used in developing new NoC architectures and captures universally accepted place-and-route methodologies. Simulation results are used to illustrate how the hardware resources of a modified Fat Tree NoC can be minimized without affecting the network performance. The performance of a NoC with regular Mesh topology was also evaluated for comparison with the modified Fat Tree topology.

Split-Gate Logic circuits for multi-threshold technologies

A new dual-Vt static CMOS circuits, the Split-Gate dual-Vt (SG-DVT) logic, are devised. Their performance is compared to that of all-low-Vt, all-high-Vt, and other dual-Vt circuits in terms of speed and energy consumption (both static and dynamic). They achieved speeds close to that of the all-low-Vt circuits, lower leakage (both stand-by and active) than other dual-Vt circuits, and lower leakage dependency on logic block input patterns.

A new FIFO design enabling fully-synchronous on-chip data communication network

A new FIFO design that enables fully synchronous circuits with unrelated clocks to communicate synchronously is proposed. Not only would every circuit be running on its own clock, but the interconnection network is fully synchronous and runs at an unrelated clock of its own. With relatively low gate count, the proposed FIFO allows communicating circuits to put/get data at their respective frequencies (1 datum/clock cycle) till it gets filled then the rates converge to the lower frequency. The maximum initial latency is 3 cycles of the consumers clock. Several manifestations of the proposed FIFO have been developed for different design cases including data width mismatch between producer and consumer. The operation of different FIFOs has been verified using gate-level simulations for several ratios of clock frequencies. An 8-cell FIFO has been designed at the transistor-level and Spice simulations using a 0.13 μm, 1.2V technology has been carried out. It shows proper operation at producer and consumer clock frequencies of 2GHz and 3.125GHz, respectively, with a data transfer rate of more than 2Giga datum/second and an average power of 721 μW.

A hardwired NoC infrastructure for embedded systems on FPGAs

A hardwired network-on-chip based on a modified Fat Tree (MFT) topology is proposed as a communication infrastructure for future FPGAs. With extremely simple routing, such an infra structure would greatly enhance the ongoing trend of embedded systems implementation using multi-cores on FPGAs. An efficient H-tree based floor plan that naturally follows the MFT construction methodology was developed. Several instances of the proposed NoC were implemented with various inter-routers links progression schemes combined with very simple router architecture and efficient client network interface (CNI). The performance of all these implementations was evaluated using a cycle-accurate simulator for various combinations of NoC sizes and traffic models. Also a new data transfer circuit for transferring data between clients and NoC operating at different (unrelated) clock frequencies has been developed. Allowing data transfer at one data per cycle, the operation of this circuit has been verified using gate-level simulations for several ratios of NoC/client clock frequencies.