Muhammad Suhaimi Sulong

Simulation study on NMOS gate length variation using TCAD tool

The process of scaling in silicon transistor has consistently resulted in smaller device geometry, higher device density and better performance. In conventional MOSFETs, control of Ioff for scaled devices requires very thin gate dielectrics and high doping concentrations. The industry roadmap predicts the barriers of continuous scaling will be due to physical limitations as well as practical technology. As the downscale of CMOS technology approaches physical limitations, the need arises for alternative device structures. Thus, this paper intends to study the effect of various gate lengths on the NMOS electrical characteristic by means of simulation study.

Small-scale monitoring system on LabVIEW platform

A simple, effective peer-to-peer networking has been developed in this paper. It serves the purpose of a two-way communication between a host and remote terminals including as an image feeder. The communication establishment is realized by means of the Laboratory Virtual Instrumentation Engineering Workbench (LabVIEW) software and internet protocol (IP) as well as the physical connection between two terminals. The system enables the user to have monitoring and control capability through the image capture and text communication. It is concluded that the system has provide an effective, low-cost way to have a monitoring and control capability in a small scale application.

Design and Simulation of Horn Antenna Using CST Software for GPR System

Detection of underground object can be made using a GPR system. This system is classified as a non-destructive technique (NDT) where the ground areas need not to be excavated. The technique used by the GPR system is by measuring the reflection of electromagnetic wave signal produced and detected by antenna which is known as the transmitter and the receiver antenna. In this study, a GPR system was studied by means of simulation using a Horn antenna as a transceiver antenna. The electromagnetic wave signal in this simulation is produced by current signal of an antenna which having a shape of modulation of Gaussian pulse which is having spectrum from 8 GHz until 12 GHz. CST and MATLAB Software are used in this GPR system simulation. A model of a Horn antenna has been designed using the CST software before the GPRs system simulation modeled by adding a model of background in front of the Horn antenna. The simulation results show that the output signal of the Horn antenna can be used in detecting embedded object which are made from material of wood and iron. In addition, the simulation result has successfully developed a 3D model image of the GPR system using output signal of the Horn antenna. The embedded iron object in the GPR system simulation can be seen clearly by using this 3D image.

Mask design, fabrication and characterization of in - house n-well MOSFET using spin -on dopant technique for undergraduates program

This paper presents a new innovative way of teaching undergraduate program using low cost masks to fabricate n-well MOSFET. The fabrication process of n-well MOSFET started with the establishment of process flow, process modules, and process parameters. The MOSFET fabrication process used blanket-field oxide for isolation, positive resist for lithography process, boron and phosphorus for source/drain doping and aluminum for metallization. An economical solution of masks using transparency films with various channel lengths from 300 µm to 500 µm has been produced to reduce cost. Six layer photolithography masks of MOSFET were designed using AutoCAD drawing tools and then printed using high resolution laser printer on the transparency film. Contact printing method has been utilized to transfer the mask layouts onto a 4-inch silicon wafer using standard photolithography techniques to check the line uniformity. Optical observation using high power microscope shows that the mask layouts were successfully transferred onto photoresist with minimum variation. The n-well CMOS transistors were tested using Keithley 2400 source meter with Lab-view measurement software. The obtained electrical characteristic is same as the theory.

Structure design challenge in Nano-CMOS device

This paper intends to report the problems and challenges that lie ahead in transistor design methodology in nano-CMOS structure. Thus, it is desired to see the options in improving the device design on top of continuing the scaling process of transistor in the next few years to come. The main concern is to see how the transistors behave as the size of device shrinks down to below 100 nm range. Besides, the demand of future generations is expected as a result of more compact of digital circuit. It is concluded that although several problems surfaces as the transistor enters the nano-CMOS era, there are excellent options to solve those problems and thus could help to reduce the transistor size and yet uncompromised the device performance.

Ashac: An alternative towards classifying the shape of aggregate

A number of image analysis applications are already available to classify the shape of aggregate. These applications were evaluated and compared with our new alternative application called aggregate shape classification system (ASHAC). This newly developed direct measurement methods have the potential to objectively classify two types of aggregate known as well-shaped (fine) aggregate and poor-shaped (coarse) aggregate. The shape properties of these aggregates used in hot-mix asphalt, hydraulic cement concrete, and unbound base and subbase layers are very important to the performance of the pavement system in which they are used in. In terms of its functionality and features, ASHAC provides more accuracy and more reliable system than others. It is an only system based on neural network using digital image processing technique. This methodology offers several advantages over current methods used in practice. Based on the overall performance, ASHAC has successfully classified the two categories of aggregate by 89.00%.