Munkyo Seo

Low Distortion 50 GSamples/s Track-Hold and Sample-Hold Amplifiers

We report 50 GSamples/s track-hold amplifier (THA) and sample-hold amplifier (SHA) designed and fabricated in a 250 nm InP double heterojunction bipolar transistor (DHBT) technology. Because the base-emitter junction reverse breakdown voltage is low in the process technology employed, the circuits use a base-collector junction diode as the switching element in the signal path. Operating with -5 V and -2.5 V supplies, the THA achieves > +16 dBm input-referred third-order intercept (IIP3) at signal frequencies below 22 GHz, while the SHA achieves IIP3 > +17 dBm for 2-22 GHz inputs.

A Wide-Locking-Range Dual Injection-Locked Frequency Divider With an Automatic Frequency Calibration Loop in 65-nm CMOS

This brief presents a wide-locking-range injection-locked frequency divider (ILFD) that uses an automatic frequency calibration loop. The proposed ILFD uses the ring oscillator to provide the high division ratio with small chip area. A dual-injection scheme is proposed in order to achieve the wide locking range of the ILFD. The free-running frequency of the ILFD is automatically digitally calibrated to reflect the frequency of the injected signal from the voltage-controlled oscillator. To control the frequency of the ILFD, the load current is digitally tuned with 3-bit control signal. The ILFD is fabricated using 65-nm CMOS process, and by tuning the load current, it achieves the wide operation frequency range of 14.1-45.8 GHz. When the input signal of 30 GHz is injected, the locking range of the ILFD is 7.2 GHz, while the power consumption is 2.5 mW from a 1-V supply voltage.

400 W broadband power amplifier using transmission-line transformers with 1:8 impedance transformation ratio

Abstract This paper presents a broadband high-power amplifier using transmission-line transformers with a high impedance transformation ratio. Two series-connected transformers with 1:8 and 1:1 impedance transformation ratios are used at the load network of a single-balanced high-power amplifier to match the low load impedance in broadband. The same transformer configuration is also used at the input network. A negative feedback is applied to improve the gain flatness and to increase the stability over the broadband. In order to validate the proposed circuit structure, a broadband high-power amplifier is designed and implemented to achieve an output power of more than 400 W in the frequency band of 30 to 500 MHz. The implemented power amplifier exhibits a flat gain response within 1.80 dB at an average of 19.1 dB and high power-added efficiencies of 28.0 to 56.9 at an output power of 400 W over the entire frequency band.

A 529 GHz Dynamic Frequency Divider in 130 nm InP HBT Process

This letter presents a 529GHz 2:1 dynamic frequency divider in a 130 nm InP HBT process, which, to the best of authors’ knowledge, is the fastest frequency divider reported thus far. The presented divider is based on a novel structure to overcome bandwidth limitations of traditional dynamic frequency divider design. On-wafer measurement shows that the divider operates with the input frequency from 528.0GHz to 529.2GHz with bias voltage tuning, while consuming PDC ≤ 196mW. A driver amplifier, integrated for testing purpose, dissipates 348mW of dc power.

A Highly Linear, Small-Area Analog Front End With Gain and Offset Compensation for Automotive Capacitive Pressure Sensors in 0.35- m CMOS

This paper presents a highly linear, small-area analog front end with gain and offset compensation for automotive capacitive pressure sensor. We propose a capacitance-tovoltage converter circuit that measures the capacitance value of the capacitive sensor with the high accuracy and linearity. In this paper, the linearity of the analog front end is guaranteed using full-analog gain and an offset calibration circuit. The proposed design is implemented using CMOS 0.35 μm technology with an active area of 1.94 mm x 1.94 mm. The full output range is from 0.5 to 4.5 V. The ratiometricity is within ±0.7% when the supply voltage is changed by ±10%. The power consumption is 25 mW from a 5 V supply. The output accuracy is within ±1% with respect to Process, Voltage, Temperature variations.

A W-Band Signal Generation Using N-Push Frequency Multipliers for Low Phase Noise

A W-band frequency generation for FMCW radar application is presented. It cascades a ring based five-push multiplier and a push-push injection-locked oscillator for 10 times multiplication with a two stage power amplifier. The chip is fabricated in 65 nm CMOS technology and its size including ESD-protected pads is 860 μm×620 μm. Phase noise of the output signal is -110 dBc/Hz at 1 MHz offset using the 7.8 GHz reference frequency with the phase noise of -132 dBc/Hz at 1 MHz offset. The output power of the complete circuit is larger than 8.8 dBm for the entire output locking range, and N-push technique enables unwanted spur suppression larger than 59 dBc. The total power consumption is 265 mW.

A 6 Gb/s Low Power Transimpedance Amplifier with Inductor Peaking and Gain Control for 4-channel Passive Optical Network in 0.13 μm CMOS

This paper presents a 6 Gb/s 4-channel arrayed transimpedance amplifiers (TIA) with the gain control for 4-channel passive optical network in 0.13 ㎜ complementary metal oxide semiconductor (CMOS) technology. A regulated cascode input stage and inductive-series peaking are proposed in order to increase the bandwidth. Also, a variable gain control is implemented to provide flexibility to the overall system. The TIA has a maximum 98.1 ㏈Ω gain and an input current noise level of about 37.8 ㎀/㎐. The die area of the fabricated TIA is 1.9 ㎜ x 2.2 ㎜ for 4-channel. The power dissipation is 47.64 ㎽/1ch.

A 130 nm InP HBT integrated circuit technology for THz electronics

A 130 nm InP HBT IC technology has been developed capable of circuit demonstrations at > 600 GHz. Transistors demonstrate RF figures-of-merit f<inf>t</inf> > 500 GHz and f<inf>max</inf> > 1 THz. The HBTs support high current densities > 25 mA/μm² with a common-emitter breakdown voltage BV<inf>ceo</inf> = 3.5 V. The technology includes a multi-level thin-film wiring environment capable of low-loss THz signal routing and high integration density. A large-signal HBT model has been developed capable of accurately predicting circuit performance at THz frequencies. Circuit demonstrations include fundamental oscillators and amplifiers operating at > 600 GHz as well as integrated transmitter and receiver circuits.

Particle simulation of electrolytic ion motions for noise in electrolyte–insulator–semiconductor field-effect transistors

We conduct particle simulation for drain current noise in electrolyte–insulator–semiconductor field-effect transistors, to simulate how the thermal motion of charged particles near the interface affects the electrical current noise in the channel. We consider three cases: bulk electrolytes without and with charged spheres located at two different distances from the electrolyte–dielectric interface. Our results show that the drain current noise from noise sources in the electrolyte can be modeled by the sum of Lorentzian spectra, whose corner frequencies are determined by the RC product of the resistances of the bulk electrolyte and the region between the charged spheres and the interface, and the capacitance of the dielectric. Also, as the charged spheres approach the electrolyte–dielectric interface, the noise level increases, in agreement with the published experimental results.

Design of a Wide-Frequency-Range, Low-Power Transceiver with Automatic Impedance-Matching Calibration for TV-White-Space Application

This paper presents a wide-frequencyrange, low-power transceiver with an automatic impedance-matching calibration for TV-white-space (TVWS) application. The wide-range automatic impedance matching calibration (AIMC) is proposed for the Drive Amplifier (DA) and LNA. The optimal S22 and S11 matching capacitances are selected in the DA and LNA, respectively. Also, the Single Pole Double Throw (SPDT) switch is integrated to share the antenna and matching network between the transmitter and receiver, thereby minimizing the systemic cost. An N-path filter is proposed to reject the large interferers in the TVWS frequency band. The current-driven mixer with a 25% duty LO generator is designed to achieve the high-gain and low-noise figures; also, the frequency synthesizer is designed to generate the wide-range LO signals, and it is used to implement the FSK modulation with a programmable loop bandwidth for multi-rate communication. The TVWS transceiver is implemented in 0.13 μm, 1-poly, 6-metal CMOS technology. The die area of the transceiver is 4 mm x 3 mm. The power consumption levels of the transmitter and receiver are 64.35 mW and 39.8 mW, respectively, when the output-power level of the transmitter is +10 dBm at a supply voltage of 3.3 V. The phase noise of the PLL output at Band 2 is -128.3 dBc/Hz with a 1 MHz offset.