Murat Askar

Real-Time Motor Fault Detection by 1-D Convolutional Neural Networks

Early detection of the motor faults is essential and artificial neural networks are widely used for this purpose. The typical systems usually encapsulate two distinct blocks: feature extraction and classification. Such fixed and hand-crafted features may be a suboptimal choice and require a significant computational cost that will prevent their usage for real-time applications. In this paper, we propose a fast and accurate motor condition monitoring and early fault-detection system using 1-D convolutional neural networks that has an inherent adaptive design to fuse the feature extraction and classification phases of the motor fault detection into a single learning body. The proposed approach is directly applicable to the raw data (signal), and, thus, eliminates the need for a separate feature extraction algorithm resulting in more efficient systems in terms of both speed and hardware. Experimental results obtained using real motor data demonstrate the effectiveness of the proposed method for real-time motor condition monitoring.

A recursive algorithm for the Bayes solution of the smoothing problem

The optimum fixed interval smoothing problem is solved using a Bayesian approach, assuming that the signal is Markov and is corrupted by independent noise (not necessarily additive). A recursive algorithm to compute the a posteriori smoothed density is obtained. Using this recursive algorithm, the smoothed estimate of a binary Markov signal corrupted by an independent noise in a nonlinear manner is determined demonstrating that the Bayesian approach presented in this paper is not restricted to the Gauss-Markov problem.

A high speed ASIC implementation of the Rijndael algorithm

In this study, a non-pipelined implementation of the Rijndael Algorithm, which is selected to be the new Advanced Encryption Algorithm (AES) by the National Institute of Standards and Technology (NIST) in October 2000, is presented. Both the encryption and the decryption algorithms of Rijndael are implemented on a single ASIC. Using 149 K gates in a 0.35-/spl mu/m standard CMOS process, we have reached a 132 MHz worst-case clock speed yielding 2.41 Gbit/s non-pipelined throughput in both encryption and decryption.

Two fast RSA implementations using high-radix montgomery algorithm

This paper presents two semi-custom VLSI implementations of 1024-bit RSA public-key cryptosystem in radix-4 and radix-16. These implementations are both based on the same design methodology, in which The R-L binary method and Montgomery algorithm are used for exponentiation and modular multiplication, respectively. The squaring and multiplication operations in the exponentiation are performed in parallel in a systolic modular multiplication unit. Both designs are implemented using AMI semiconductor 0.35 /spl mu/m CMOS technology. Radix-4 implementation resulted in 3.97 ns worst-case clock period with /spl sim/n/sup 2/ worst-case number of cycles (237 Kbps) and 132 K gate count. Radix-16 implementation resulted in 5.1 ns worst-case clock period with /spl sim/n/sup 2//2 worst-case number of cycles (377 Kbps) and 155 K gate count.

Practical performance of planar spiral inductors

Inductors are essential elements for RF design. For RFIC design, bondwires, planar solenoidal and planar spiral inductors are available. Due to some limitations of bondwires and planar solenoidal inductors, planar spiral inductors are the most popular ones. Designers try to get accurate lumped element models for planar spiral inductors in order to be able to simulate the circuit performance correctly before the integrated circuit is manufactured. Planar spiral inductor measurement methods are discussed, and the comparison between lumped element model simulation results and experimental measurement results are given. The results of this study show that it is possible to model planar spiral inductors with lumped element circuit models, parameters of which can be calculated by basic, but accurate, expressions.

A high speed FPGA implementation of the Rijndael algorithm

This paper presents a high speed, non-pipelined FPGA implementation of the Rijndael algorithm (Daemen, 1999), which has been selected as the new AES algorithm by the National Institute of Standards and Technology (NIST). In this study, we have implemented both the encryption and the decryption algorithms of Rijndael on the same FPGA. All the key and data length combinations of the original Rijndael algorithm are supported. This implementation, which uses 8378 slices and 4 block RAMs of the Xilinx FPGA, has a worst case operating frequency of 65 MHz, yielding a maximum throughput of 1.19 Gb/s.

Turkish small satellite program: Goals and policies

Abstract Information Technologies and Electronics Research Institute (BILTEN) has initiated a low-earth orbit small satellite project in Turkey. This project is part of a program to achieve expertise on satellite related technologies. The main goal of the project is to transfer technology on building small satellites. For the realization of the project an international contractor will be named. The contractor will be responsible of a technology transfer program as well as manufacture and launch of a small satellite with prescribed missions. The details of this program is given and explained. Information regarding BILTEN is also given.

Optimal sequential smoothing with uncertain observations

Bayes optimal recursive algorithms that do not require growing memory are obtained for the problems of fixed-interval, fixed-point and fixed-lag smoothing with uncertain observations. It is assumed that the signal sequence to be estimated is Markov and that the observations may contain the noise alone or the signal corrupted by noise (not necessarily additive). The uncertainty in the observations is governed by a Markov sequence, and the observation noise is an independent sequence. Under these assumptions, recursive algorithms are devised for the a posteriori density ƒ(Xk \ YN ), for the three types of smoothing problem. The algorithms also yield a detection scheme of the sequential likelihood ratio test type, as to the presence or absence of the signal at each observation. The Bayes fixed-interval smoothing algorithm is applied to a Gauss-Markov example. The simulation results for this example indicate that the MSE performance of the Bayes smoother is significantly better than that of the linear smoother.

Recursive algorithms for the Bayes solution of the fixed-point and fixed-lag smoothing problems

Recursive algorithms for the Bayes solutions of the fixed-point and fixed-lag smoothing problems are obtained. Recursive algorithms for the respective smoothed a posteriori densities are derived under assumptions that the signal to be estimated is a Markov process and the observation is a signal embedded in independent noise (not necessarily additive) which is also independent of the signal. The recursive algorithm for the fixed-point smoothing is applied to a binary Markov signal corrupted by an independent noise in a nonlinear manner.

8×8-Bit multiplier designed with a new wave-pipelining scheme

In this paper, a new wave-pipelining scheme is proposed. In classical wave-pipelining scheme, the data waves propagate on the circuit and the propagating waves are sampled simultaneously when they reach to a synchronization stage. In this new wave-pipelining scheme, only the components of the wave whose delay-difference values reach to a critical value are sampled. Other components, which are not sampled, are aligned with the sampled ones by using active delay elements. This wave-pipelining scheme significantly decreases the number of flip-flops which are used to synchronize the propagating waves. For demonstrating the effectiveness of the new wave-pipelining scheme, an 8×8-bit carry save multiplier is implemented using 0.35um standard CMOS process. Simulation results show that, the multiplier can operate at a speed of 2GHz, by using only 55 flip-flops. Comparing with the mesochronous pipelining scheme, the number of the flip-flops is decreased by 47%.