Murat Ceven

Implementation of PSK and QAM demodulators on FPGA

Communication is possible if the signal from transmitter is demodulated properly in the receiver and the quality of the communication depends on the accuracy of demodulation. In this study, a digital receiver building is developed in order to demodulate variable symbol rate PSK or QAM modulated signal in a nosiy channel under carrier and symbol timing error conditions. According to this purpose a digital demodulator is designed and implemented on a Xilinx Virtex-4SX35 FPGA board. FPGA Design stages and simulation results of developed model are presented in this paper.

IP Header Reduction for APCO Project-25 data links

In this study we examine IP Header Reduction, the term we use for an approach which aims to reduce the IP Header for a specific point-to-point narrow band APCO Project-25 data links. The goal is to investigate opportunities for improving the utilization of IP connectivity on limited bandwidth link resources. We define and propose a simple protocol and messaging format. Its a software process which will run on both side of data links with its functionality. We also define communication protocol and message format which is used by these processes for intercommunication. Example scenario given in this study provides the idea behind how IP Header Reduction is realized. At the end of the study, potential bandwidth gain is calculated and produced at specified condition. It will be seen that especially for some limited bandwidth real time control or sensor data transfer applications which require small size but frequent data transfer, can significantly benefit from implementation of this study.

Reception of C4FM and CQPSK signals in APCO Project-25

In the first phase of APCO Project-25, Phase-I, the C4FM modulation is defined for the transmission, with a bandwidth of 12.5 kHz. However in Phase-II, CQPSK modulation based transmission is defined with the bandwidth of 6.25 kHz to increase spectral efficiency. This results in a receiver structure in Phase-II, which is capable of demodulating both C4FM and CQPSK signals so that backward compatibility is obtained with Phase-I signals. While this common demodulator facilitates a single receiver structure, on the other hand frequency demodulator based structure becomes unavoidable for CQPSK. In this paper, we propose a complete receiver structure for APCO P-25. The proposed receiver structure consists of four major units; frequency discriminator, frame synchronization, sampling phase and sample clock offset correction, and frequency offset recovery units. This structure is realized in computer environment and BER performances of both modulations are evaluated under various multipath fading channel, sampling clock error, and frequency offset error conditions.

Data mode optimization management for APCO Project-25 data networks

APCO Project-25 wireless data link is a Narrow Band wireless link. This causes communicataion link to have very limited bandwidth which is between from 4 kbps up to 7.2 kbps. In such case we are in search of every opportunity to improve and well-utilize this low-bandwidth channel for data communications. In this paper we study two data communication modes of APCO Project-25 Data Communication structure and offer to change these modes dynamically to improve efficiency. APCO Project-25 Data Communication Modes are; 1. Confirmed Communication and 2. Unconfirmed Communication. For Confirmed Communication Mode, all packets are protected by 3/4 Trellis Code and for each packet received, other party sends confirmation package. For Uncofirmed Communication Mode, 1/2 Trellis Code is used for protection and there is no acknowledgement. In both modes, each packet has its CRC information. Based CRC success/fail statistics, system will decide to switch to other in order to increase bandwidth or provide robustness of communication.

Implementation of polyphase-FFT based channelizer on FPGA

In this paper a channelizer implementation is performed on FPGA by first a demonstration through simulation and then by applying real test signals. In this study, polyphase FFT based method is selected as the channelization method. The wideband signal, with the bandwidth of 50 MHz, is sampled by 105 MHz and divided into 64 channels with the channel spacing of 0.82 MHz while each one has a sampling frequency of 1.64 MHz and complex outputs. The filter that discriminates between channels has a bandwidth of 1 MHz which allows a certain degree of interference between the adjacent channels, enabling the derivation of signals existing at the intersection area of these channels. In order to realize this, two times oversampling is used for each channel. The design is first simulated in MATLAB environment, and then coded in VHDL and simulated in ModelSim environment. After simulations, the design is synthesized in Xilinx-ISE and loaded to the development board with Virtex-4SX35 FPGA on it, for further testing with real signals.