Murat Tuna

Effective and Reliable Speed Control of Permanent Magnet DC (PMDC) Motor under Variable Loads

This paper presents the effective and reliable speed control of PMDC motors under variable loads and reference speeds. As is known DC motors are more preferred in industrial practices. This is that, the PMDC motors don’t require brush and commutator care and to increase in torque per motor depending on developments in power electronics. In this study, proportional-integral controller (PI) and fuzzy logic controller (FL) have been designed for speed control of PMDC motor. In the design of these controllers, characteristics such as minimum overrun time, response time to the load, settling time and ideal rise time have been taken into consideration for better stability performance. In this design, the best system response was searched by examining the effect of different defuzzification methods onto the fuzzy logic system response. In conclusion, it has been seen that FL controller has a better performance for variable speed-load control of PMDC motor compared to PI controller.

Edge dedection application with FPGA based Sobel operator

Image processing can be defined as analysis of the images consists of the several steps. The edge detection process that is one of these steps can be performed using a variety of operators. Sobel edge detection operator, is a basic operator, is preferred to use with high noisy images because its corruption is insensible on images. The proposed work presents an edge detection algorithm using Sobel operator based on FPGA architecture. Proposed system is designed using IEEE 754-1985 floating-point standard and VHDL hardware description language. Design is synthesized for Xilinx Virtex-6 FPGA chip with 160 MHz operating frequency. The performance is decreed according chip statistics.

Real time implementation of a novel chaotic generator on FPGA

In this study, a new continuous-time autonomous chaotic system has been presented and implemented on FPGA. Presented a new chaotic system has been designed using the IEEE 754-1985 floating-point format and implemented using Heun algorithm with VHDL language. The designed system has been synthesized and tested on Xilinx Virtex-6 FPGA chip. According to the test results, operation frequency of the FPGA-based a new chaotic signal generator is certain as 390 MHz and performance results have been given with chip statistics. In addition, the results obtained from FPGA-based new chaotic generator have been compared with the Matlab-based numerical results and it has been observed that obtained results are successful. By the developed FPGA-based novel chaotic system model, chaos-based various engineering applications such as true random number generation and secure communication system can be performed.

Real time hardware implementation of the 3D chaotic oscillator which having golden-section equilibra

In this study, the continuous-time, autonomous, 3D chaotic system having golden-section equilibra which is recently presented in the literature is implemented firstly as discrete time on an FPGA. In this design, the 3D chaotic system was programmed in 32-bit IQ-Math (16I-16Q) fixed-point number format using VHDL and Heun algorithm. The designed system has been synthesized and tested, using Xilinx ISE design tool, on Virtex-6 FPGA chip. According to the test results, operation frequency of the FPGA-based new chaotic signal generator is certain as 406.736MHz. In addition, chip statistics and performance results of the new chaotic oscillator are presented after the “Route&Place” processes performed on Xilinx ISE design tool. The chaotic oscillator design realized with fixed-point number format on FPGA has been shown to be use lesser chip hardware and higher operating frequency compared to the floating-point standard.