Murray Pearson

Three simulator tools for teaching computer architecture: Little Man computer, and RTLSim

Teaching computer architecture (at any level) is not an easy task.To enhance learning, a critical mass of educators has begun usingsimulator visualizations of different computer architectures. Herewe present three representative computer architecture simulatorsfor learning which show that there is a growing consensus forcomputer simulation as a teaching tool for complex dynamicprocesses, such as underlying computer operations. Simulators alsoshow the wide spectrum of pedagogical goals for teaching computerorganization and architecture. Specifically, the three simulatorswe describe are (1) EasyCPU for the Intel 80x86 family of CPUs; (2)Little Man Computer for a general von Neumann computerarchitecture; and (3) RTLSim, a data path simulator for a MIPS-likeCPU. An appendix is provided for more detailed descriptions of eachsimulator.

Distributed expertise for teaching computer organization & architecture

This report presents preliminary results from our project on creating distributed expertise for teaching computer organization & architecture course(s) in the undergraduate computer science curriculum. We present the details of an online survey designed to gather information from faculty on the current state of teaching this course. The survey also tries to identify specific areas of need for creating distributed expertise as reported by various faculty. We also present several resources that have been identified that are available for use by faculty teaching the course(s). This report represents a mid-point of an ongoing two-year study. Following a discussion of the currently identified needs, we discuss ways to address them and conclude the report with a plan of action that will follow in the next phase of the project.

High precision traffic measurement

Making passive measurements is a challenging process. A small number of research groups have overcome these difficulties and have made terabytes of captured network traffic available to the Internet community. We have discovered that even when initial hurdles to collecting traces have been overcome, there are potentially many methodological weaknesses that can severely limit the usefulness of the data collected. This article describes these weaknesses and suggests methodologies to avoid them. Five case studies from the work of the University of Waikatos WAND network research group are presented. These studies illustrate the need for care at all stages of the measurement process, analysis, and presenting the results.

Multi-campus teaching using computer networks

This paper describes a joint project between hlassey and li7izilufo Universities to investigate the potential of ATM in providing telepresence in distance education situations. In 1997, Massey and W’aikato, offered a graduate level paper jointly between the two campuses. Teaching on this course in advanced computer architecture was delivered in bodl qnchromm and aryzch.ronous modes, with some lectures being recorded at Massey and sen~ed m the web via the ATM network to Waikuto, and other lectures being delivered live across the A1’M network using iWPEG hardware compression cards. The course was well accepted despite the non-comentiocal presentation techniques

The architecture of an optimistic CPU: the WarpEngine

The architecture for a shared memory CPU is described. The CPU allows for parallelism down to the level of single instructions and is tolerant of memory latency. All executable instructions and memory accesses are time stamped. The TimeWarp algorithm is used for managing synchronisation. This algorithm is optimistic and requires that all computations can be rolled back. The basic functions required for implementing the control and memory system used by TimeWarp are described. The memory model presented to the programmer is a single linear address space modified by a single thread of control. Thus, at the software level there is no need for explicit synchronising actions when accessing memory. The physical implementation, however, is multiple CPUs with their own caches and local memory with each CPU simultaneously executing multiple threads of control.<<ETX>>

Design of a processor to support the teaching of computer systems

Teaching computer systems, including computer architecture, assembly language programming and operating system implementation, is a challenging occupation. At the University of Waikato this is made doubly true because we require all computer science and information systems students study this material at second year. The challenges of teaching difficult material to a wide range of students have driven its to find ways of making the material more accessible. The cornerstone of our strategy for delivering this material is the design and implementation of a custom CPU that meets the needs of teaching. This paper describes our motivation and these needs. We present the CPU and board design and describe the implementation of the CPU in an FPGA. The paper also includes some reflections on the use of a real CPU rather than a simulation environment. We conclude with a discussion of how the CPU can be used for advanced classes in computer architecture and a description of the current status of the project.

Timestamp representations for virtual sequences

The problem of executing sequential programs in parallel using the optimistic algorithm Time Warp is considered. This is done by first mapping the sequential execution to a control tree and then assigning timestamps to each node in the tree.For such timestamps to be effective in either hardware or software they must be finite, this implies that they must be periodically rescaled to allow old timestamps to be reused. A number of timestamp representations are described and compared on the basis of: their complexity; the frequency and cost of rescaling; and the cost of performing basic operations, including comparison and creation of new timestamps.

A Rapid Prototyping Platform for Wireless Medium Access Control Protocols

Packet broadcast networks are in widespread use in modern wireless communication systems and medium access control (MAC) is a key functionality within these. Substantial research effort has been and continues to be invested into the study of existing protocols and the development of new and specialised ones, however researchers are restricted in their studies by an absence of suitable wireless MAC protocol development methods. We describe a platform which allows rapid prototyping and evaluation of wireless medium access control protocols, based around a field programmable gate array (FPGA) with embedded processor, and an IEEE 802.11b-compatible transceiver. The hardware architecture along with supporting firmware and software provides for a short design cycle in implementation of custom MAC protocols, and a large degree of flexibility in hardware/software co-design trade-offs. Measurement and evaluation are integral to the system design with facilities for accurate time-stamping within the hardware, and ability to synchronise timing across physically distributed nodes using the Global Positioning System (GPS). The architecture allows measurement within a node which is actively participating in a network.

Using custom hardware and simulation to support computer systems teaching

Teaching computer systems, including computer architecture, assembly language programming and operating systems implementation, is a challenging occupation. At the University of Waikato we require all computer science and information systems students study this material at second year. The challenges of teaching difficult material to a wide range of students have driven us to find ways of making the material more accessible. The corner-stone of our strategy for delivering this material is the design and implementation of a custom CPU that meets the needs of teaching. In addition to the custom CPU we have developed several simulators that allow specific topics to be studied in detail. This paper describes our motivation for devloping a custom CPU and supporting tools. We present our CPU and the teaching board and describe the implementation of the CPU in an FPGA. The simulators that that have been developed to support the teaching of the course are then described. The paper concludes with a description of the current status of the project.

Applying Time Warp to CPU design

This paper exemplifies the similarities in Time Warp and computer architecture concepts and terminology, and the continued trend for convergence of ideas in these two areas. Time Warp can provide a means to describe the complex mechanisms being used to allow the instruction execution window to be enlarged. Furthermore it can extend the current mechanisms, which do not scale, in a scalable manner. The issues involved in implementing Time Warp in a CPU design are also examined, and illustrated with reference to the Wisconsin Multiscalar machine and the Waikato WarpEngine. Finally the potential performance gains of such a system are briefly discussed.