Mury Thian

A 76–84 GHz SiGe Power Amplifier Array Employing Low-Loss Four-Way Differential Combining Transformer

This paper presents holistic design of a novel four-way differential power-combining transformer for use in millimeter-wave power-amplifier (PA). The combiner with an inner radius of 25 μm exhibits a record low insertion loss of 1.25 dB at 83.5 GHz. It is designed to simultaneously act as a balanced-to-unbalanced converter, removing the need for additional BALUNs typically required in differential circuits. A complete circuit comprised of a power splitter, two-stage differential cascode PA array, a power combiner as well as input and output matching elements was designed and realized in SiGe technology with fT/fmax 170/250 GHz. Measured small-signal gain of at least 16.8 dB was obtained from 76.4 to 85.3 GHz with a peak 19.5 dB at 83 GHz. The prototype delivered 12.5 dBm output referred 1 dB compression point and 14 dBm saturated output power when operated from a 3.2 V dc supply voltage at 78 GHz.

High-Efficiency Harmonic-Peaking Class-EF Power Amplifiers With Enhanced Maximum Operating Frequency

The recently introduced Class-EF power amplifier (PA) has a peak switch voltage lower than that of the Class-E PA. However, the value of the transistor output capacitance at high frequencies is typically larger than the required Class-EF optimum shunt capacitance. Consequently, soft-switching operation that minimizes power dissipation during off-to-on transition cannot be achieved at high frequencies. Two new Class-EF PA variants with transmission-line load networks, namely, third-harmonic-peaking (THP) and fifth-harmonic-peaking (FHP) Class-EF PAs are proposed in this paper. These permit operation at higher frequencies at no expense to other PA figures of merit. Analytical expressions are derived in order to obtain circuit component values, which satisfy the required Class-EF impedances at fundamental frequency, all even harmonics, and the first few odd harmonics as well as simultaneously providing impedance matching to a 50- Ω load. Furthermore, a novel open-circuit and shorted stub arrangement, which has substantial practical benefits, is proposed to replace the normal quarter-wave line connected at the transistors drain. Using GaN HEMTs, two PA prototypes were built. Measured peak drain efficiency of 91% and output power of 39.5 dBm were obtained at 2.22 GHz for the THP Class-EF PA. The FHP Class-EF PA delivered output power of 41.9 dBm with 85% drain efficiency at 1.52 GHz.

Analysis and Design of Class-E

In this paper, analysis and synthesis approach for two new variants within the Class-EF power amplifier (PA) family is elaborated. These amplifiers are classified here as Class-E3 F and transmission-line (TL) Class-E 3F 2. The proposed circuits offer means to alleviate some of the major issues faced by existing topologies such as substantial power losses due to the parasitic resistance of the large inductor in the Class-EF load network and deviation from ideal Class-EF operation due to the effect of device output inductance at high frequencies. Both lumped-element and transmission-line load networks for the Class-E 3F PA are described. The load networks of the Class-E3 F and TL Class-E3 F2 amplifier topologies developed in this paper simultaneously satisfy the Class-EF optimum impedance requirements at fundamental frequency, second, and third harmonics as well as simultaneously providing matching to the circuit optimum load resistance for any prescribed system load resistance. Optimum circuit component values are analytically derived and validated by harmonic balance simulations. Trade-offs between circuit figures of merit and component values with some practical limitations being considered are discussed.

_{3}

A newly introduced inverse class-E power amplifier (PA) was designed, simulated, fabricated, and characterized. The PA operated at 2.26 GHz and delivered 20.4-dBm output power with peak drain efficiency (DE) of 65% and power gain of 12 dB. Broadband performance was achieved across a 300-MHz bandwidth with DE of better than 50% and 1-dB output-power flatness. The concept of enhanced injection predistortion with a capability to selectively suppress unwanted sub-frequency components and hence suitable for memory effects minimization is described coupled with a new technique that facilitates an accurate measurement of the phase of the third-order intermodulation (IM3) products. A robust iterative computational algorithm proposed in this paper dispenses with the need for manual tuning of amplitude and phase of the IM3 injected signals as commonly employed in the previous publications. The constructed inverse class-E PA was subjected to a nonconstant envelope 16 quadrature amplitude modulation signal and was linearized using combined lookup table (LUT) and enhanced injection technique from which superior properties from each technique can be simultaneously adopted. The proposed method resulted in 0.7% measured error vector magnitude (in rms) and 34-dB adjacent channel leakage power ratio improvement, which was 10 dB better than that achieved using the LUT predistortion alone.

F and Transmission-Line Class-E

The design and characterizations of an ultrafast single-pole single-throw (SPST) absorptive differential switch are presented. The switch exhibits low insertion loss less than 1 dB, and isolation better than 16 dB from 40 to 70 GHz. Sub-nanosecond switching time is achieved by adopting a differential current-steering technique. The total measured rise and fall time are 75 ps envisaging that switching rates up to 13 Gb/s are achievable. To our best knowledge, this is the fastest, lowest insertion loss V-band SPST switch yet reported that can operate over a wide bandwidth of 30 GHz.

_{3}

This paper presents an ultrafast wideband low-loss single-pole double-throw (SPDT) differential switch in 0.35 m SiGe bipolar technology. The proposed topology adopting current-steering technique results in a total measured switching time of 75 ps , which suggests a maximum switching rate of 13 Gb/s, the fastest ever reported at V-band. In addition, the switch exhibits an insertion loss lower than 1.25 dB and an isolation higher than 18 dB from 42 GHz to 70 GHz.

F

A novel Class-E power amplifier (PA) topology with transmission-line load network is presented in this brief. When compared with the classic Class-E topology, the new circuit can increase the maximum operating frequency up to 50% higher without trading the other Class-E figures of merit. Neither quarterwave line/massive radio-frequency choke for collector/drain biasing nor additional fundamental-frequency output matching circuit are needed in the proposed PA, thus resulting in a compact design. Closed-form formulations are derived and verified by simulations with practical design limitations carefully taken into consideration and good agreement achieved.

_{2}

A recently introduced power-combining scheme for a Class-E amplifier is, for the first time, experimentally validated in this paper. A small value choke of 2.2 nH was used to substitute for the massive dc-feed inductance required in the classic Class-E circuit. The power-combining amplifier presented, which operates from a 3.2-V dc supply voltage, is shown to be able to deliver a 24-dBm output power and a 9.5-dB gain, with 64% drain efficiency and 57% power-added efficiency at 2.4 GHz. The power amplifier exhibits a 350-MHz bandwidth within which a drain efficiency that is better than 60% and an output power that is higher than 22 dBm were measured. In addition, by adopting three-harmonic termination strategy, excellent second- and third-harmonic suppression levels of 50 and 46 dBc, respectively, were obtained. The complete design cycle from analysis through fabrication to characterization is explained.

Power Amplifiers

An analysis of a modified series- L / parallel-tuned Class-E power amplifier is presented, which includes the effects that a shunt capacitance placed across the switching device will have on Class-E behaviour. In the original series L /parallel-tuned topology in which the output transistor capacitance is not inherently included in the circuit, zero-current switching (ZCS) and zero-current derivative switching (ZCDS) conditions should be applied to obtain optimum Class-E operation. On the other hand, when the output transistor capacitance is incorporated in the circuit, i.e. in the modified series- L /parallel-tuned topology, the ZCS and ZCDS would not give optimum operation and therefore zero-voltage-switching (ZVS) and zero-voltage-derivative switching (ZVDS) conditions should be applied instead. In the modified series- L /parallel-tuned Class-E configuration, the output-device inductance and the output-device output capacitance, both of which can significantly affect the amplifiers performance at microwave frequencies, furnish part, if not all, of the series inductance L and the shunt capacitance C OUT , respectively. Further, when compared with the classic shunt- C /series-tuned topology, the proposed Class-E configuration offers some advantages in terms of 44% higher maximum operating frequency ( f MAX ) and 4% higher power output capability ( P MAX ). As in the classic topology, the f MAX of the proposed amplifier circuit is reached when the output-device output capacitance furnishes all of the capacitance C OUT , for a given combination of frequency, output power and DC supply voltage. It is also shown that numerical simulations agree well with theoretical predictions.

Digital Baseband Predistortion Based Linearized Broadband Inverse Class-E Power Amplifier

In this brief, we propose a new class-E frequency multiplier based on the recently introduced series-L/parallel-tuned class-E amplifier. The proposed circuit produces even-order output harmonics. Unlike previously reported solutions the proposed circuit can operate under 50% duty ratio which minimizes the conduction losses. The circuit also offers the possibility for increased maximum operating frequency, reduced peak switch voltage, higher load resistance and inherent bond wire absorption; all potentially useful in monolithic microwave integrated circuit implementations. In addition, the circuit topology suggested large transistors with high output capacitances can be deployed. Theoretical design equations are given and the predictions made using these are shown to agree with harmonic balance circuit simulation results.