Mustafa Altun

Logic Synthesis for Switching Lattices

This paper studies the implementation of Boolean functions by lattices of four-terminal switches. Each switch is controlled by a Boolean literal. If the literal takes the value 1, the corresponding switch is connected to its four neighbors; else it is not connected. A Boolean function is implemented in terms of connectivity across the lattice: it evaluates to 1 iff there exists a connected path between two opposing edges of the lattice. The paper addresses the following synthesis problem: how should one assign literals to switches in a lattice in order to implement a given target Boolean function? The goal is to minimize the lattice size, measured in terms of the number of switches. An efficient algorithm for this task is presented-one that does not exhaustively enumerate paths but rather exploits the concept of Boolean function duality. The algorithm produces lattices with a size that grows linearly with the number of products of the target Boolean function in ISOP form. It runs in time that grows polynomially. Synthesis trials are performed on standard benchmark circuits. The synthesis results are compared to a lower-bound calculation on the lattice size.

Lattice-based computation of Boolean functions

This paper studies the implementation of Boolean functions with lattices of two-dimensional switches. Each switch is controlled by a Boolean literal. If the literal is 1, the switch is connected to its four neighbours; else it is not connected. Boolean functions are implemented in terms of connectivity across the lattice: a Boolean function evaluates to 1 iff there exists a top-to-bottom path. The paper addresses the following synthesis problem: how should we map literals to switches in a lattice in order to implement a given target Boolean function? We seek to minimize the number of switches. Also, we aim for an efficient algorithm - one that does not exhaustively enumerate paths. We exploit the concept of lattice and Boolean function duality. We demonstrate a synthesis method that produces lattices with a number of switches that grows linearly with the number of product terms in the function. Our algorithm runs in time that grows polynomially.

Realisation of nth order current transfer function employing ECCIIs and application examples

In this article, a universal nth-order current-mode filter employing electronically tunable second-generation current conveyors (ECCIIs) and grounded passive elements is proposed. As the current gain of the ECCII can be controlled electronically by adjusting the ratio of its DC bias currents, it is possible to tune all the coefficients of the transfer function independently. SPICE simulation results using TSMC 0.35 μm CMOS process model are included to verify the theory. Furthermore, a design example of a fourth-order video band filter is given to illustrate the application of the introduced topology in analog circuit design.

Nanoscale digital computation through percolation

In this study, we apply a novel synthesis technique for implementing robust digital computation in nanoscale lattices with random interconnects: percolation theory on random graphs. We exploit the non-linearity that occurs through percolation to produce Boolean functionality. We show that the error margins, defined in terms of the steepness of the non-linearity, translate into the degree of defect tolerance. We study the problem of mapping Boolean functions onto lattices with good error margins.

Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays

This paper studies fault tolerance in switching reconfigurable nano-crossbar arrays. Both permanent and transient faults are taken into account by independently assigning stuck-open and stuck-closed fault probabilities into crosspoints. In the presence of permanent faults, a fast and accurate heuristic algorithm is proposed that uses the techniques of index sorting, backtracking, and row matching. The algorithm’s effectiveness is demonstrated on standard benchmark circuits in terms of runtime, success rate, and accuracy. In the presence of transient faults, tolerance analysis is performed by formally and recursively determining tolerable fault positions. In this way, we are able to specify fault tolerance performances of nano-crossbars without relying on randomly generated faults that is relatively costly regarding that the number of fault distributions in a crossbar grows exponentially with the crossbar size.

Logic synthesis and testing techniques for switching nano-crossbar arrays

Abstract Beyond CMOS, new technologies are emerging to extend electronic systems with features unavailable to silicon-based devices. Emerging technologies provide new logic and interconnection structures for computation, storage and communication that may require new design paradigms, and therefore trigger the development of a new generation of design automation tools. In the last decade, several emerging technologies have been proposed and the time has come for studying new ad-hoc techniques and tools for logic synthesis, physical design and testing. The main goal of this project is developing a complete synthesis and optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. New models for diode, FET, and four-terminal switch based nanoarrays are developed. The proposed methodology implements logic, arithmetic, and memory elements by considering performance parameters such as area, delay, power dissipation, and reliability. With combination of logic, arithmetic, and memory elements a synchronous state machine (SSM), representation of a computer, is realized. The proposed methodology targets variety of emerging technologies including nanowire/nanotube crossbar arrays, magnetic switch-based structures, and crossbar memories. The results of this project will be a foundation of nano-crossbar based circuit design techniques and greatly contribute to the construction of emerging computers beyond CMOS. The topic of this project can be considered under the research area of “Emerging Computing Models” or “Computational Nanoelectronics”, more specifically the design, modeling, and simulation of new nanoscale switches beyond CMOS.

Computing with Emerging Nanotechnologies

As current CMOS based technologies are approaching their anticipated limits, emerging nanotechnologies start to replace their role in electronic circuits. New computing models have been proposed. This chapter overviews both deterministic and stochastic computing models targeting nano-crossbar switching arrays and emerging low-density circuits. These models are demonstrated with implementations using Boolean and arithmetic logic. Performance parameters of the models such as area, speed, and accuracy, are also evaluated in comparison with those of conventional circuits.

Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays

In this study, we introduce an accurate capacitor-resistor model for nano-crossbar arrays that is to be used for power/delay/area performance analysis and optimization. Although the proposed model is technology independent, we explicitly show its applicability for three different nanoarray technologies where each crosspoint behaves as a diode, a FET, and a four-terminal switch. In order to find related capacitor and resistor values, we investigate upper/lower value limits for technology dependent parameters including doping concentration, nanowire dimension, pitch size, and layer thickness. We also use different fan-out capacitors to test the integration capability of these technologies. Comparison between the proposed model and a conventional simple one, which generally uses one/two capacitors for each crosspoint, demonstrates the necessity of using our model in order to accurately calculate power and delay values. The only exception where both models give approximately same results is the presence of considerably low valued resistive connections between switches. However, we show that this is a rare case for nano-crossbar technologies.

A change-point based reliability prediction model using field return data

In this study, we propose an accurate reliability prediction model for high-volume complex electronic products throughout their warranty periods by using field return data. Our model has a specific application to electronics boards with given case studies using 36-month warranty data. Our model is constructed on a Weibull-exponential hazard rate scheme by using the proposed change point detection method based on backward and forward data analysis. We consider field return data as short-term and long-term corresponding to early failure and useful life phases of the products, respectively. The proposed model is evaluated by applying it to four different board data sets. Each data set has between 1500 and 4000 board failures. Our prediction model can make a 36-month (full warranty) reliability prediction of a board with using its field data as short as 3 months. The predicted results from our model and the direct results using full warranty data match well. This demonstrates the accuracy of our model. We also evaluate our change point method by applying it to our board data sets as well as to a well-known heart transplant data set.

Warranty forecasting of electronic boards using short-term field data

The main goal of our study is precisely predicting the reliability performance of electronic boards throughout the warranty period by using short-term field return data. We have cooperated with one of the Europes largest manufacturers and use their well-maintained data with over 1000 electronic board failures. Before using the field data for our model of warranty forecasting, we filter it to eliminate improper data, correlated to incomplete and poorly collected data. Our model is based on a two-parameter Weibull distribution, chosen from many other distribution options regarding optimum curve fitting. In the fitting process we use and compare “Bayesian”, “rank regression”, and “maximum likelihood” fitting techniques. Our method has two steps. In the first step, we investigate how the Weibull parameter β changes by increasing the number of months of field data. For this purpose we use an electronic board with 36 months (full warranty period) of field return data. We develop a mathematical model of β as a function of the field data time interval and board dependent parameters. In the second step, we make a warranty forecasting of a new electronic board using its 3-month field data by using the mathematical model developed in the first step. The proposed method is evaluated by applying it to different electronic boards with 36 months (full warranty period) of field return data. The predicted results from our method and the direct results from the field return data matches well. This demonstrates the accuracy of our model.