Mustafa Gök

Efficient Cell Designs for Systolic Smith-Waterman Implementations

Smith-Waterman algorithm is used to search bioinformatics databases. The systolic array implementations of this algorithm can search databases hundreds of times faster than software applications. The performances of the systolic Smith-Waterman implementations mainly depend on the number of cells they contain and the clock frequencies of the cells. This paper presents efficient cell designs for systolic Smith-Waterman implementations. The designs that use the presented cells and the recent reference designs are mapped on the same FPGA platform and compared by syntheses. Syntheses results show that the performance of the presented designs are 1.7 to 3.6 times higher than the reference designs.

Multi-functional floating-point MAF designs with dot product support

This paper presents multi-functional double-precision and quadruple-precision floating-point multiply-add fused (FPMAF) designs. The double-precision FPMAF design can execute adouble-precision floating-point multiply-add, or two single-precision floating-point multiplications, or a single-precision floating-point dot product. The quadruple-precision FPMAF can perform similar operations with quadruple, double and single precision operands. These architectures can perform a dot-product operation two times or more faster than a basic FPMAF design. The presented multi-functional designs are compared with basic double-precision and quadruple-precision FPMAF designs by ASIC syntheses. The syntheses results show that the proposed double-precision implementation has 8%more area than a standard double-precision FPMAF implementation, and the proposed quadruple-precision design has 12.5% more area than a standard quadruple-precision FPMAF. Both of the proposed designs have one more pipeline stage compared to the basic designs.

A multi-precision floating-point adder

This paper presents a multi-precision floating-point adder that can perform a high-precision floating-point addition, or multiple low-precision floating-point additions in parallel. The proposed design eliminates time consuming format conversion operations when it is operating in low-precision modes. The proposed multi-precision floating-point adder has delay approximately equal to a standard double-precision floating-point adder.

Carotid Intima-Media Thickness as the Cardiometabolic Risk Indicator in Patients with Nonfunctional Adrenal Mass and Metabolic Syndrome Screening

Background Our purpose was to show the association of adrenal incidentaloma and metabolic syndrome in consideration of the studies and to detect the increase in the carotid intima-media thickness which is regarded as the precessor of atherosclerosis. Material/Methods Eighty-one patients who were diagnosed with adrenal mass were included in the study. Hormonal evaluation, insulin rezistance measurement with the HOMA-IR and 1-mg DST were performed of all patients. The patients were classified as follows: mass size <3 cm (K1) and mass size of at least 3 cm (K2). Echocardiography and carotid intima-media thickness of the patients were measured using B-mode ultrasound. Thirty-three healthy individuals were enrolled as the control group. Results Mass size of 64.19% K1, while mass size of the remainder (35.81%) K2 was calculated. Five of the patients with adrenal mass were detected to have subclinical Cushing syndrome. The remaining 76 patients were accepted as nonfunctional. It was seen with regard to metabolic and biochemical parameters that plasma glucose (p=0.01), insulin (p=0.00) and triglyceride (p=0.012) values of all patients were significantly high compared to those of the control group. It was detected that measured heart rate (p=0.00), end-diastolic diameter (p=0.02), end-systolic diameter (p=0.014) and carotid intima-media thickness (p=0.00) values of the patients with adrenal mass were significantly higher than those of the healthy control group. Conclusions We found that the increased insulin resistance, increased risk of cardiovascular disease with the increase in the thickness of carotid intima-media and diastolic disfunction parameters, although the patients with adrenal incidentaloma are nonfunctional.

A novel IEEE rounding algorithm for high-speed floating-point multipliers

Modern floating-point multipliers perform rounding in compliance with the IEEE 754 standard. Since rounding is on the critical path, high-speed rounding algorithms are used to increase the performance for floating-point multiplication. To achieve high performance with minimum increase in hardware, existing rounding algorithms generate two consecutive values in parallel, and compute the rounded product using these values. This paper presents a novel IEEE rounding algorithm which generates two nonconsecutive values in parallel to compute the rounded product. Synthesis results for double precision operands show that the proposed algorithm has approximately 24-41% less delay than previous high-speed rounding algorithms presented elsewhere. The verification of the new algorithm is also presented in a simple and straightforward manner.

A demand based route generation algorithm for public transit network design

This paper presents a public transit network route generation algorithm. The main contribution of this work is the introduction of new route generation algorithms. The proposed route generation algorithm is tested on Mandl@?s Swiss Road network and the four large networks presented in recent previous work. Three parameters are used to evaluate the route sets generated by the proposed algorithm. These are the zero transfer percentage, the average travel time, and the total route cost. The route sets generated for the large networks have better parameter values compared to recent previous work.

Pipelined Large Multiplier Designs on FPGAs

Large multiplication is widely used in modern cryptography systems, multimedia and signal processing applications. This paper presents three pipelined large multiplier (PLM) design methods that use specialized multiplier logic provided in modern FPGA platforms. The presented design methods provide efficient usage of symmetric multiplier resources. Also, they can be used to map a large multiplier even on a small size FPGA. The syntheses results show that a pipelined 256-bit multiplier implemented in this paper uses 15 times less DSP slices on a Virtex 5 xc5vfx100t FPGA than a monolithic multiplier mapped on the same FPGA. The trade off is a three times reduction in the speed in this specific case.

Integer squarers with overflow detection

Squaring is commonly used in digital signal processing applications. Significant performance increase can be achieved by supporting squaring in hardware. This paper presents overflow detection methods applicable to integer squarers with unsigned and twos complement operands. These methods are unified for a combined squarer design. Presented methods can be applied to any squarer independent of size and architecture. The proposed squarer designs have approximately 50% less area and delay compared to the conventional squarer designs with overflow detection.

Sequential Large Multipliers on FPGAs

Large operands are used in modern cryptography, signal processing and multimedia applications. Multiplication is one of the most used operations in these applications. The multiplication of the large operands is performed by a large multiplier hardware to achieve high speed. These circuits can be designed by using embedded arithmetic blocks offered by the state of the art FPGAs. In this paper, sequential large multiplier designs that can be mapped on these platforms are presented. Three design algorithms are proposed which differ depending on the use of the FPGA resources. 64-bit to 2048-bit multiplier implementations for these algorithms are modeled and synthesized. Compared to a fully combinational 256-bit multiplier the proposed 256-bit multiplier uses 15 times less resources and has 1.94 times more delay.

A Public Transit Network Route Generation Algorithm

Abstract Route generation task in a public transit network is a complex combinatorial problem which cannot be manually solved. This paper presents a computer algorithm for the solution of this problem. The presented algorithm has a novel initialization procedure. The algorithm is implemented and tested on Mandls Swiss Road network [Mandl, 1979]. Extensive test runs of the proposed algorithm on this network show that the proposed algorithm has better average travel times in all cases except one and offers up to 23% cost savings compared to the most recent work [Fan and Mumford, 2010].