Mustafa Mert Torunbalci

A Bulk-Micromachined Three-Axis Capacitive MEMS Accelerometer on a Single Die

This paper presents a high-performance three-axis capacitive microelectromechanical system (MEMS) accelerometer implemented by fabricating individual lateral and vertical differential accelerometers in the same die. The fabrication process is based on the formation of a glass-silicon-glass multi-stack. First, a 35-μm (111) silicon structural layer of an Silicon-On-Insulator (SOI) wafer is patterned with deep reactive ion etching (DRIE) and attached on a base glass substrate with anodic bonding, whose handle layer is later removed. Next, the second glass wafer is placed on the top of the structure not only for allowing to implement a top electrode for the vertical accelerometer, but also for acting as an inherent cap for the entire structure. The fabricated three-axis MEMS capacitive accelerometer die measures 12 × 7 × 1 mm3. The x-axis and y-axis accelerometers demonstrate measured noise floors and bias instabilities equal to or better than 5.5 μg/√Hz and 2.2 μg, respectively, while the z-axis accelerometer demonstrates 12.6 μg/√Hz noise floor and 17.4 μg bias instability values using hybrid-connected fourth-order sigma-delta CMOS application specific integrated circuit (ASIC) chips. These low noise performances are achieved with a measurement range of over ±10 g for the x-axis and y-axis accelerometers and +12/-7.5 g for the z-axis accelerometer, suggesting their potential use in navigation grade applications.

Advanced MEMS Process for Wafer Level Hermetic Encapsulation of MEMS Devices Using SOI Cap Wafers With Vertical Feedthroughs

This paper reports a novel and inherently simple fabrication process, so-called advanced MEMS (aMEMS) process, that is developed for high-yield and reliable manufacturing of wafer-level hermetic encapsulated MEMS devices. The process enables lead transfer using vertical feedthroughs formed on an Silicon-On-Insulator (SOI) wafer without requiring any complex via-refill or trench-refill processes. It requires only seven masks to fabricate the hermetically capped sensors with an experimentally verified process yield of above 80%. Hermetic encapsulation is achieved by Au-Si eutectic bonding at 400 °C, and the pressure inside the encapsulated cavity has been characterized to be as low as 1 mTorr with successfully activated thin-film getters. The pressure inside the encapsulated cavity can also be adjusted in the range of 1 mTorr-5 Torr by various combinations of outgassing and gettering options in order to satisfy the requirements of different applications. The package pressure is being monitored for the selected chips and is observed to be stable below 10 mTorr since their fabrication about 10 months ago. The shear strengths of several packages are measured to be as high as 30 MPa with average shear strength of 22 MPa, indicating a mechanically strong bonding. The robustness of the packages is tested by thermal cycling between 100 °C and 25 °C, and absolutely no degradation is observed in the hermeticity and the package pressure. The package pressure is also verified to remain unchanged after storing the packages at a high storage temperature of 150 °C for 24 h. Furthermore, the packaged chips are observed to withstand a high temperature shock test performed at 300 °C for 5 min, at the end of which the characteristics of the encapsulated sensor indicates that the package still remains hermetic (no detectable leaks) and also the package pressure remains constant at ~20 mTorr.

Wafer level hermetic encapsulation of MEMS inertial sensors using SOI cap wafers with vertical feedthroughs

This paper reports a new, inherently simple, and high-yield wafer-level hermetic encapsulation method developed for MEMS inertial sensors, enabling lead transfer using vertical feedthroughs that do not require any complex via-refill or trench-refill processes. The process requires only seven masks to complete both the sensor and cap wafers, whereas the combined yield for the sealing and lead transfer is experimentally verified to be above 90%. Hermetic encapsulation is achieved by Au-Si eutectic bonding, and the pressure inside the encapsulated cavity has been characterized to be as low as 1 mTorr with a thin film getter. MEMS resonators packaged with the proposed method demonstrated quality factors over 125,000. The pressure inside the encapsulated cavities has been monitored for 4 months since the first prototypes, and it is observed to be stable throughout this period.

A method and electrical model for the anodic bonding of SOI and glass wafers

This paper provides a method for the anodic bonding of SOI and glass wafers, and it explains the bonding mechanism with an electrical model, for the first time in the literature. SOI-glass anodic bonding can be achieved at voltages as low as 250 V similar to Si-glass anodic bonding, and the underlying principles can be understood by modeling the overall system with a series-connected capacitor-resistor network. The SOI-oxide layer can be added as a capacitor to the classical anodic bonding model, and the behavior of the bonding can be estimated with the basic circuit theory. The oxide capacitance in the model acts as a short circuit at the time instant when the bonding potential is applied, and then it gradually becomes an open circuit. The model is also successfully adapted to triple stack glass-Si-glass anodic bonding, which enables wafer level packaging and offers many opportunities to MEMS designers.

A novel fabrication and wafer level hermetic sealing method for SOI-MEMS devices using SOI cap wafers

This paper presents a novel and inherently simple all-silicon fabrication and hermetic packaging method developed for SOI-MEMS devices, enabling lead transfer using vertical feedthroughs formed on an SOI cap wafer. The processes of the SOI cap wafer and the SOI-MEMS wafer require a total of five inherently-simple mask steps, providing a combined process and packaging yield as high as 95%. The hermetic encapsulation is achieved by Au-Si eutectic bonding at 400°C. The package pressure is measured as 1 Torr without any getter activation, and the package is proved to remain hermetic even after various temperature cycling tests. The shear strength of the fabricated chips is measured to be above 15 MPa, indicating a mechanically strong bonding.

Gold-tin eutectic bonding for hermetic packaging of MEMS devices with vertical feedthroughs

This paper presents a new method for wafer-level hermetic encapsulation of MEMS devices using low-temperature (280 to 300°C) Au-Sn eutectic bonding applied to the recently developed advanced MEMS (A-MEMS) process of the METU-MEMS Research Center, which uses an SOI cap wafer with vertical feedthroughs that does not need any complex via-refill or trench-refill process steps. The Au-Sn eutectic bonding process is achieved at 300°C with a bond pressure of 2 MPa by using a sealing alloy thickness less than 1.5 μm. The package pressure is characterized to be around 250 mTorr, without any getter activation. The remelting temperature of the Au-Sn bonding interface is measured by using differential scanning calorimetry (DSC) analysis and found to be around 280°C, verifying that the bonding is achieved at the desired eutectic composition (80% Au and 20% Sn), also confirmed by the energy dispersive X-ray spectroscopy (EDS) analysis. The shear strengths of several packages are measured to be above 20 MPa, indicating a mechanically-strong bonding. The robustness of the packages is also tested by subjecting them to high temperature storage at 200°C for 24 hours, and no degradation is observed in the hermeticity of the packages at the end of this period.

A method for wafer level hermetic packaging of SOI-MEMS devices with embedded vertical feedthroughs using advanced MEMS process

This paper presents a novel, inherently simple, and low-cost fabrication and hermetic packaging method developed for SOI-MEMS devices, where a single SOI wafer is used for the fabrication of MEMS structures as well as vertical feedthroughs, while a single glass cap wafer is used for hermetic encapsulation and routing metallization. Hermetic encapsulation can be achieved either with the silicon-glass anodic or Au–Si eutectic bonding techniques. The dies sealed with anodic and Au–Si eutectic bonding provide a low vertical feedthrough resistance around 50 Ω. Glass-to-silicon anodically and Au–Si eutectic bonded seals yield a very stable cavity pressure below 10 mTorr with thin-film getters, which are measured to be stable even after 311 d. The package pressure can be adjusted from 5 mTorr to 20 Torr by using different outgassing, cavity depth, and gettering options. The packaging yield is observed to be around 64% and 84% for the anodic and Au–Si eutectic packages, respectively. The average shear strength of the anodic and eutectic packages is measured to be higher than 17 MPa and 42 MPa, respectively. Temperature cycling, high temperature storage, and ultra-high temperature shock tests result in no degradation in the hermeticity of the packaged chips, proving perfect thermal reliability.

Die size reduction by optimizing the dimensions of the vertical feedthrough pitch and sealing area in the advanced MEMS (aMEMS) process

This paper presents the recent reduction of the die size by 44% in the Advanced MEMS (aMEMS) process, now being compatible in size with most of the available through-wafer packaging processes while offering the unique simplicity of the aMEMS process. Size reduction is achieved by reducing the pitch of vertical feedthroughs from 700 μm down to 350 μm and the bonding area width from 300 μm down to 100 μm, approaching to the process limits and still preserving the hermeticity of the package. Both small and large dies, containing the identical resonance sensors inside for benchmarking, are produced together on the same wafer. The cavity pressures of the both dies are measured to be around 1 mTorr even after thermal cycling tests.

Fabrication and characterization of gold-tin eutectic bonding for hermetic packaging of MEMS devices

This paper presents the fabrication of wafer-level hermetic encapsulation for MEMS devices using low-temperature (300°C) Au-Sn bonding together with their pre- and postbonding characterization. Thermal evaporation method was used for metallization which is easy and controllable method for low thickness metallization. In this respect, the current study represents preliminary characterization results of Au-Sn pre- and post-bonding with an average thickness of less than 1.5μm processed by thermal evaporation method. The real fabrication conditions for commercial sensor devices were simulated during the bonding trials. The optimum bonding was applied to sensor devices to ensure the reliability of the encapsulation. The average shear-strength upon constant strain rate of 0.5 mm.min-1 was found to be around 23 MPa which indicates a mechanically strong bonding for 1.5μm thick sealing rings.

The advanced MEMS (aMEMS) process for fabricating wafer level vacuum packaged SOI-MEMS devices with embedded vertical feedthroughs

This paper presents a novel, inherently simple and low-cost fabrication and hermetic packaging method developed for SOI-MEMS devices, where an SOI wafer is used for the fabrication of MEMS structures as well as vertical feedthroughs, while a glass cap wafer is used for hermetic encapsulation and routing metallization. Glass-to-silicon anodically bonded seals yield a very stable cavity pressure of 150 mTorr after 15 days. The shear strength of the fabricated packages is above 7 MPa. Temperature cycling and ultra-high temperature shock tests results in no degradation in the hermeticity of the packaged chips.