Mutlu Avci

A hybrid classification method of k nearest neighbor, Bayesian methods and genetic algorithm

k Nearest neighbor, Bayesian methods and genetic algorithms are effective methods of machine learning. In this work a hybrid method is formed by using these methods and algorithm together. The aim is to achieve successful results on classifying by eliminating data that make difficult to learn. Forming new data set approach is proposed according to good data on the hand. Test process is done with five of UCI machine learning datasets. These are iris, breast cancer, glass, yeast and wine data sets. Test results are investigated in collaboration with the previous works, and the success of the study is considered.

Accurate SPICE compatible CNT interconnect and CNTFET models for circuit design and simulation

Abstract SPICE compatible CNT interconnect and CNTFET models in Verilog-A hardware description language are presented in this paper. Metallic CNTs are shown to have current saturation characteristics above a threshold voltage and then modelled with piecewise linear functions. On the other hand, the CNTFET model developed utilizes the calculation of the self-consistent potential of the CNT channel depending on gate and drain voltages. Unlike the previous SPICE-enabled CNTFET models using approximations and curve fittings, the proposed model employs a self-consistent method for the calculation of the channel potential in SPICE, providing more accuracy. The versatility of the CNT interconnect model and that of the CNTFET model are shown in CNT circuit simulations.

Neural network based MOS transistor geometry decision for TSMC 0.18μ process technology

In sub-micron technologies MOSFETs are modeled by complex nonlinear equations. These equations include many process parameters, terminal voltages of the transistor and also the transistor geometries; channel width (W) and length (L) parameters. The designers have to choose the most suitable transistor geometries considering the critical parameters, which determine the DC and AC characteristics of the circuit. Due to the difficulty of solving these complex nonlinear equations, the choice of appropriate geometry parameters depends on designer’s knowledge and experience. This work aims to develop a neural network based MOSFET model to find the most suitable channel parameters for TSMC 0.18μ technology, chosen by the circuit designer. The proposed model is able to find the channel parameters using the input information, which are terminal voltages and the drain current. The training data are obtained by various simulations in the HSPICE design environment with TSMC 0.18μm process nominal parameters. The neural network structure is developed and trained in the MATLAB 6.0 program. To observe the utility of proposed MOSFET neural network model it is tested through two basic integrated circuit blocks.

Neural network modeling of voltage-dependent resistance of metallic carbon nanotube interconnects: An ab initio study

In this work, development voltage-dependent resistance models of metallic carbon nanotubes for computer aided design tools is aimed. Firstly, the resistance of metallic carbon nanotube interconnects are obtained from first principles simulations and the voltage dependence of the resistance is modeled through neural networks. Self-consistent non-equilibrium Greens function formalism combined with density functional theory is used for calculating the voltage-dependent resistance of metallic carbon nanotubes. It is shown that voltage dependent resistances of carbon nanotubes obtained from ab initio simulations can be accurately modeled via neural networks which enable rapid integration of carbon nanotube interconnect models into electronic design automation tools.

An improved Elmore delay model for VLSI interconnects

Elmore delay metric is a widely used model to compute signal delays for both analog and digital circuit interconnects. Although it provides a limited accuracy and its applicability is limited to the step function type input signals, this model is extremely popular with simple analytical functions that can be easily incorporated into design and automation software. In this work, a new boundary limiting the Elmore delay is introduced. A general form of traditional Elmore delay is defined and solved by utilizing this boundary. The new solution of the propagation delay problem called the improved Elmore delay model is derived according to the compound interest problem of Jacob Bernoulli. The improved Elmore delay formulation and the traditional Elmore delay model are compared according to SPICE simulation environment performances which verifies the superior accuracy of the novel delay formulation. The test results proved that better accuracy is achieved with the improved Elmore delay model than the traditional Elmore delay model with the same computation speed.

Neural network reinforced point defect concentration estimation model for Czochralski-grown silicon crystals

The point defects are the most important and fundamental components of silicon microdefects. Modeling and estimation of their concentration has ever increasing importance. In this work, a simplified model for the vacancy type and self-interstitial-type defects is considered. The problem of the model is explained and a neural network reinforced improvement is adapted to the model. The improved analytical model is compared with the finite volume technique based numerical solution on an application. Finally it is observed that the model gained better accuracy and validity with the aid of a neural network. All simulations are done in MATLAB environment and the results are concluded.

Performance comparison of different momentum techniques on deep reinforcement learning

ABSTRACT Recently, the popularity of deep artificial neural networks has increased considerably. Generally, the method used in the training of these structures is simple gradient descent. However, training a deep structure with simple gradient descent can take quite a long time. Some additional approaches have been utilized to solve this problem. One of these techniques is the momentum that accelerates gradient descent learning. Momentum techniques can be used for supervised learning as well as for reinforcement learning. However, its efficiency may vary due to the dissimilarities in two learning processes. While the expected values of inputs are clearly known in supervised learning, it may take long-running iterations to reach the exact expected values of the states in reinforcement learning. In an online learning approach, a deep neural network should not memorize and continue to converge with the more precise values that exist over time during these iterations. For this reason, it is necessary to use a momentum technique that both adapt to reinforcement learning and accelerate the learning process. In this paper, the performance of different momentum techniques is compared with the Othello game benchmark. Test results show that the Nesterov momentum technique provided a more effective generalization with an online reinforcement learning approach.

Performance comparision of different momentum techniques on deep reinforcement learning

Increase in popularity of deep convolutional neural networks in many different areas leads to increase in the use of these networks in reinforcement learning. Training a huge deep neural network structure by using simple gradient descent learning can take quite a long time. Some additional learning approaches should be utilized to solve this problem. One of these techniques is use of momentum which accelerates gradient descent learning. Although momentum techniques are mostly developed for supervised learning problems, it can also be used for reinforcement learning problems. However, its efficiency may vary due to the dissimilarities in two training learning processes. In this paper, the performances of different momentum techniques are compared for one of the reinforcement learning problems; Othello game benchmark. Test results show that the Nesterov accelerated momentum technique provided a more effective generalization on benchmark

The intelligent memory allocator selector

Memory fragmentation is a serious obstacle preventing efficient memory usage. Garbage collectors may solve the problem; however, they cause serious performance impact, memory and energy consumption. Therefore, various memory allocators have been developed. Software developers must test memory allocators, and find an efficient one for their programs. Instead of this cumbersome method, we propose a novel approach for dynamically deciding the best memory allocator for every application. The proposed solution tests each process with various memory allocators. After the testing, it selects an efficient memory allocator according to condition of operating system (OS). If OS runs out of memory, then it selects the most memory efficient allocator for new processes. If most of the CPU power was occupied, then it selects the fastest allocator. Otherwise, the balanced allocator is selected. According to test results, the proposed solution offers up to 58% less fragmented memory, and 90% faster memory operations. In average of 107 processes, it offers 7.16?2.53% less fragmented memory, and 1.79?7.32% faster memory operations. The test results also prove the proposed approach is unbeatable by any memory allocator. In conclusion, the proposed method is a dynamic and efficient solution to the memory fragmentation problem. HighlightsOur solution is an intelligent memory allocator selector for operating systems.The solution selects an efficient and fastest memory allocator for each process.The approach reduces memory fragmentation, and increases system performance.Our solution is a dynamic and efficient solution to memory fragmentation problem.

A coding method for 123 decision diagram pass transistor logic circuit synthesis

Pass transistor logic (PTL) circuits are known for their smaller silicon area usage, low power consumption and reduced delay advantages. The 123 decision diagram is a very effective PTL synthesis tool based on binary decisions. It realizes a logic function using NMOS pass transistors with CMOS restoring buffers. At the same time, layout of the circuit for a two metal process is obtained by this diagram. A special coding is required to apply the 123 decision diagram. Until now, the coding for the diagram has not been explained. In this paper, a very easy and effective coding method for circuit synthesis and simplification with 123 decision diagrams is proposed.