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Dive into the research topics where Myeong-Hwan Lee is active.

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Featured researches published by Myeong-Hwan Lee.


IEEE Transactions on Consumer Electronics | 1994

A new algorithm for interlaced to progressive scan conversion based on directional correlations and its IC design

Myeong-Hwan Lee; Jeong-Hoon Kim; Jeong-Sang Lee; Kyeong-Keol Ryu; Dong-Il Song

Current TV systems suffer from uncomfortable visual artifacts such as edge flicker, interline flicker and line crawling, due to the inherent nature of the interlaced scanning process. Besides, the increasing demands of large TV screens have turned the problem of reducing visible line structures in a TV screen into an important issue. To lessen the visual affects of those artifacts, a technique known as an interlaced to progressive conversion (IPC) technique has been widely studied in various shapes. In the paper, the authors propose a new algorithm for interlaced to progressive conversion, referred to as a directional correlation dependent interpolation filtering (DIF) algorithm, which is composed of a correlation-dependent linear interpolation for a signal in the low horizontal frequency band and a line doubling method for a signal lying in the high horizontal frequency band. The DIF algorithm splits the horizontal frequency band of a given input 2D signal into two adjoint signals and applies two isolated interpolation schemes for the respective bands. In the algorithm, the authors develop a directional correlation dependent, interpolation technique depending on the spatial correlations between the spatially symmetric samples in the observation sliding window centered at the sample to be estimated. Computer simulations and the hardware implementation of the proposed algorithm to evaluate its performance are rigorously evaluated. The authors design a chip for luminance/chrominance interpolation with peaking process (YCIP) which has been tested with a real sequence of LDP images. >


international conference on acoustics speech and signal processing | 1996

A new survivor memory management method in Viterbi decoders: trace-delete method and its implementation

Suk-Jin Jung; Myeong-Hwan Lee; Hyung-Jin Choi

The well known methods for survivor path storage and decoding are the register-exchange method (REM) and the trace-back method (TBM). The REM is conceptually simple, but it is not appropriate for VLSI implementation because it requires large power consumption and large chip area. The TBM is the preferred method in the VLSI implementation of Viterbi decoders (VD) having large constraint length and high performance. However, the TBM requires last-in-first-out (LIFO) buffer and has to use multiple read operations for high speed operation. This multiple operation results in complex control logic. In this paper, we propose a new survivor memory management method called trace-delete method (TDM) and realize this algorithm in hardware (H/W) for VLSI implementation and we compare the TDM with the TBM in terms of latency, the number of memory elements, and the requirements of control logic. The main advantage of the proposed method can be found as short latency and less requirements on additional control logic. Especially, if we combine the TDM with block interleaving the implementation is even simpler than the TBM. The method is studied with particular relevance to HDTV.


IEEE Transactions on Broadcasting | 1994

A new ghost cancellation system for Korean GCR

Ki-Bum Kim; Jinsung Oh; Myeong-Hwan Lee; Humor Hwang; Dong-Il Song

This paper describes a new ghost cancellation system built-in NTSC television based on the Korean ghost cancellation reference (KGCR) signal. The system has a highly integrated transversal filter, an unique circuit for control of the system and a high performance algorithm for calculating the filter coefficients. Laboratory and field test results confirm that the system is effective in canceling several combination of ghosts, which exist in real situations. >


international conference on consumer electronics | 1997

Development Of A Digital FPLLl ASIC For GA HDTV Receivers

Dong-Seog Han; Myeong-Hwan Lee; Kil-Houm Park

We propose a new digital carrier recovery loop architecture for the Grand Alliance high definition television (HDTV) system. We have developed an application specific integrated circuit (ASIC) based on the new architecture. The developed ASIC has a gate count of 60 K with a gate array technology that features 0.5 /spl mu/m, 3.3 V and 2-metal-layer technology. The pull-in range of the proposed architecture is about /spl plusmn/250 kHz with 0 dB carrier-to-noise ratio (CNR).


global communications conference | 1996

A new survivor memory management method in Viterbi decoders

Suk-Jin Jung; Myeong-Hwan Lee; Hyung-Jin Choi

In this paper, we propose a new survivor memory management method called the trace-delete method (TDM). Hardware (H/W) realization of the proposed algorithm for VLSI implementation is considered. Comparison of the TDM with the trace-back method (TBM) is also provided in terms of latency, the number of memory elements, and the requirements of control logic. The main advantages of the proposed method are short latency and less requirements on additional control logic. The performance is also evaluated when the method is applied to the Grand Alliance HDTV system.


international conference on consumer electronics | 1999

A design of VSB receiver IC for digital television

Jisung Oh; Yongduk Chang; Hyun-Soo Shin; Myeong-Hwan Lee; Ki-Burn Kim

This paper describes a single ASIC chip that demodulates and decodes vestigial side band (VSB) digital TV signals. The VSB IC has been implemented for the receiver based on the ATSC digital TV standard. It can be applied to both modes of signal reception-8 VSB for terrestrial broadcast and 16 VSB for cable transmission.


IEEE Transactions on Consumer Electronics | 1997

Hybrid LCD panel system and its color coding algorithm

Myeong-Hwan Lee; Han-il Ko; Dong-Il Song

A color liquid crystal display (LCD) panel typically used in consumer products is composed of R, G, and B subpixels. Due to the subpixel structure and color microfilters, a single LCD panel system (SLPS) using such a panel has a low resolution, low brightness, and a poor appearance of the individual color pixel elements. These problems are solved by having a three LCD panel system (TLPS) which is composed of three black/white (B/W) LCD panels. However, this system requires high cost and high hardware (H/W) complexity. We propose a new LCD system using B/W and color LCD panels called the hybrid LCD panel system (HLPS) to overcome the drawbacks of other types of LCD panel applications. Also, the associated color coding algorithm for maximizing the effect of the proposed system is developed. In spite of using the simplified H/W structure, little visual difference has been attained in comparison with the TLPS in the terms of the resolution and brightness, and the color fidelity is better than the SLPS. Among the three types of the LCD projector, the 7.34% light utilization efficiency of the HLPS is the highest. Also, the HLPS is compact and relatively inexpensive.


IEEE Transactions on Consumer Electronics | 1997

CSD filter design for VLSI implementation of GA-VSB receiver

Myeong-Hwan Lee

We present several filters for the Grand Alliance (GA) vestigial sideband (VSB) receiver. Especially, we design the digital filters for the digital frequency and phase lock loop (DFPLL), which can be easily integrated in a single VLSI chip, with limited bit length coefficients using canonic signed digit (CSD) code and evaluate the performance of the designed filters by comparing the frequency characteristics with the real coefficient filters. The CSD code conversion is a class of quantization in which the filter coefficients are quantized. A filter represented by a CSD code is called the CSD filter. The quantized coefficients which are restricted to the set of representable numbers by and digit CSD code with 2 nonzero digit (L=2, M=7) are considered. In spite of the simplified hardware (H/W) structure for implementation, it is shown that the CSD filters attain little difference compare to the case of real filters using real coefficients. When we select SEC STD60, the ASIC implementation of filters for the DFPLL using CSD filters requires about 30/spl sim/35 K gates.


international conference on asic | 1997

VSB demodulator ASIC design and development for HDTV system

Myeong-Hwan Lee; Dong-Suk Han; Hyun-Soo Shin; Ki-Bum Kim; Dong-Il Song; Du Nguyen; Steve Ku; Sung-Sam Im

In this paper, we present ASIC design and implementation of vestigial sideband (VSB) demodulator for high definition television (HDTV) system employing the VSB modulation technique. We present three ASIC chips for VSB demodulator implementation.


international conference on consumer electronics | 1995

Development of a wide TV system equipped with 2/3 vertical expansion

S.O. Park; Jae-seung Sung; Jun-Rae Kim; Jeong-Hoon Kim; Myeong-Hwan Lee; Tae-Hong Jeong

We have developed a new TV system equipped with a digital filter which expands a given 4:3 image vertically at the rate of 2/3 to fit into a 16:9 wide monitor leading to a pleasing visual quality. The algorithm for enlarging an image vertically can be classified in two categories: deflection and digital signal processing. The digital signal processing scheme is employed to overcome the shortcomings introduced by the deflection scheme, and it maintains the resolution of the image with a good quality.

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Dongkyu Kim

Korea Institute of Science and Technology

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