Myung-Ho Jung

Transmission Electron Microscopy and Raman-Scattering Spectroscopy Observation on the Interface Structure of Graphene Formed on Si Substrates with Various Orientations

Graphene can be grown on three major low-index substrates of Si(111), (110), and (001) by forming a 3C-SiC thin film and by subliming Si atoms from the top few layers of the SiC film. We have investigated the structure of graphene/3C-SiC interface by cross-sectional transmission electron microscopy (XTEM) and Raman-scattering spectroscopy. While the interface layer quite similar to that on the graphene/6H-SiC(0001) face is found to exist on the 3C-SiC(111)/Si(111) substrate, no such interface structure exists on the (110)- and (001)-oriented faces.

High-Performance Graphene Field-Effect Transistors With Extremely Small Access Length Using Self-Aligned Source and Drain Technique

Self-aligned source/drain (S/D) graphene field-effect transistors (GFETs) with extremely small access lengths were successfully fabricated using a simple device fabrication process without sidewall spacer formation. The self-aligned S/D GFET exhibits superior electrical characteristics, such as the intrinsic carrier mobility of 6100 cm2/Vs, the gate leakage current of 10-10-10-9 A and the contact resistance of 412 Ωμm. In particular, a cutoff frequency of 13 GHz was achieved with a rather large gate length (LG= 3 μm), which demonstrates the promising future of this self-aligned GFET.

Site-Selective Epitaxy of Graphene on Si Wafers

The fusion of graphene with silicon may provide an effective solution to the problem of scale in electronic devices. This approach will allow the excellent electronic properties of graphene to be combined with known Si device technologies. We review the epitaxial growth of graphene on Si substrates (GOS) for fabricating transistors. GOS has been multifunctionalized by controlling the orientation of the Si substrate. The site-selective epitaxy of GOS has also been developed by controlling the base SiC thin films. These results demonstrate that GOS is suitable for integrated devices.

Polymer Material as a Gate Dielectric for Graphene Field-Effect-Transistor Applications

Epitaxial-graphene field-effect transistor (EG-FET) with a polymer gate dielectric was fabricated and their electrical characteristics were investigated. The epitaxial graphene layer was formed on a semi-insulating 6H-SiC substrate by a high-temperature annealing in ultrahigh vacuum. The formation of graphene was confirmed by low-energy electron diffraction (LEED), Raman-scattering spectroscopy and X-ray photoelectron spectroscopy (XPS). The polymer gate dielectric (ZEP520a) layer was formed by spin coating, which exhibits good dielectric properties without noticeable structural degradation of the graphene layer. The EG-FETs with this polymer gate dielectric shows an n-type characteristic, with the field-effect mobility of 580 cm2 V-1 s-1.

Charge Trapping Characteristics of Variable Oxide Thickness Tunnel Barrier with SiO2/HfO2 or Al2O3/HfO2 Stacks for Nonvolatile Memories

Charge trapping characteristics of asymmetrical tunnel barriers consisting of different dielectric materials were investigated for application of nonvolatile memory devices. A thin HfO2 layer stacked on ultrathin SiO2 layer (SiO2/HfO2 tunnel barrier) revealed higher current sensitivity to applied gate voltage than the conventional single SiO2 tunnel barrier. On the other hand, the electron trapping of the tunnel barriers increased with the thickness of HfO2 layer. Thus, a thin HfO2 layer is promising for the engineered tunnel barriers, while a thick HfO2 layer is appropriate for charge trapping layers for high-integrated nonvolatile memories. Meanwhile, an ultrathin Al2O3/HfO2 tunnel barrier also revealed good electrical characteristics and is suitable for low temperature fabrication process.

Correlation of an infrared absorption with carriers in rare-earth monoantimonides

Abstract Dielectric constants spectra were obtained in the single crystals LaSb, PrSb, GdSb and DySb at several temperatures. The spectra for these crystals except for LaSb show Drudes behavior with a hump due to an anomalous absorption lying at about 0.25 eV. The inverse of effective electron number ( N IA ) of the absorption is linear in temperature, and the N IA at each temperature is dependent on the square of the effective Bohr magneton of each rare-earth ion. The sum of the number of effective electrons due to Drude adsorption and that due to infrared absorption agree well with the number of carriers obtained from their band calculations or their dHvAs. Therefore, this absorption seems to be due to the intraband transition induced by the scattering between the spin of carriers and the localized magnetic moments at each site of rare-earth ion.

Tunneling Properties in High-k Insulators with Engineered Tunnel Barrier for Nonvolatile Memory

The metal-insulator-silicon (MIS) capacitors with and high-k dielectrics (, ) were fabricated, and the current-voltage characteristics were investigated. Especially, an effective barrier height between metal gate and dielectric was extracted by using Fowler-Nordheim (FN) plot and Direct Tunneling (DT) plot of quantum mechanical(QM) modeling. The calculated barrier heights of thermal , ALD , and are 3.35 eV, 0.6 eV, 1.75 eV, and 2.65 eV, respectively. Therefore, the performance of non-volatile memory devices can be improved by using engineered tunnel barrier which is considered effective barrier height of high-k materials.

Improved Electrical Characteristics of Symmetrical Tunneling Dielectrics Stacked with SiO 2 and Si 3 N 4 Layers by Annealing Processes for Non-volatile Memory Applications

The electrical characteristics and annealing effects of tunneling dielectrics stacked with and were investigated. I-V characteristics of band gap engineered tunneling gate stacks consisted of (NON), (ONO) dielectrics were evaluated and compared with single layer using the MOS (metal-oxide-semiconductor) capacitor structure. The leakage currents of engineered tunneling barriers (ONO, NON stacks) are lower than that of the conventional single layer at low electrical field. Meanwhile, the engineered tunneling barriers have larger tunneling current at high electrical field. Furthermore, the increased tunneling current through engineered tunneling barriers related to high speed operation can be achieved by annealing processes.

Degradation of electrical characteristics in Bio-FET devices by O 2 plasma surface treatment and improving by heat treatment

The effects of surface treatment by plasma on the Bio-FETs were investigated by using the pseudo-MOSFETs on the SOI substrates. After a surface treatment by plasma with different RF powers, the current-voltage and field effect mobility of pseudo-MOSFETs were measured by applying back gate bias. The subthreshold characteristics of pseudo-MOSFETs were significantly degraded with increase of RF power. Additionally, a forming gas anneal process in 2 % diluted ambient was developed to recover the plasma process induced surface damages. A considerable improvement of the subthreshold characteristics was achieved by the forming gas anneal. Therefore, it is concluded that the pseudo-MOSFETs are a powerful tool for monitoring the surface treatment of Bio-FETs and the forming gas anneal process is effective for improving the electrical characteristics of Bio-FETs.