Myung-Jun Choe

An 8-b 100-MSample/s CMOS pipelined folding ADC

When applied to folding ADCs, pipelining relieves the wide bandwidth requirement of the folding amplifier. A pipelined folding ADC prototyped using a 0.5 /spl mu/m CMOS process exhibits a DNL of /spl plusmn/0.4 LSB and an INL of /spl plusmn/1.3 LSB at 100 MSample/s. The chip occupies 1.4 mm/spl times/1.2 mm in active area and consumes 165 mW at 5 V.

A 1.6-GS/s 12-bit return-to-zero GaAs RF DAC for multiple Nyquist operation

RZ current switches are added to a current steering DAC for high-frequency wideband applications to achieve 800MHz bandwidth at 1/sup st/ and 2/sup nd/ Nyquist band without the need for a reverse sinc equalization filter. Implemented in a GaAs HBT process with 4.5 /spl mu/m/sup 2/ minimum emitter area, the DAC dissipates 1.2W at -5V with a 1.6GHz clock and 0dBm typical output power.A 12-bit 1.6-GS/s digital-to-analog converter (DAC) implemented with 4-/spl mu/m/sup 2/ GaAs HBT process is presented. Return-to-zero (RZ) current switches are added to current steering DAC for high-frequency wideband applications to achieve 800-MHz bandwidth at first and second Nyquist band without the need for a reverse sinc equalization filter in wideband transmitter application. The RZ circuit also improves spectral purity by screening the switching noise from the analog output during data transition. Measured performance shows two-tone third-order harmonic distortion of -70 dB at 1.5-GHz output frequency, clocked at 1.6 GHz. Reliable interface with CMOS logic IC is guaranteed with the inclusion of a four-clock-deep FIFO circuit. The DAC dissipates 1.2 W at -5 V when sampled with 1.6-GHz clock, with typical output voltage swing of 1.2 V/sub PP/.

High Performance Mixed Signal and RF Circuits Enabled by the Direct Monolithic Heterogeneous Integration of GaN HEMTs and Si CMOS on a Silicon Substrate

In this work we present recent results on the direct heterogeneous integration of GaN HEMTs and Si CMOS on a silicon substrate. GaN HEMTs whose DC and RF performance are comparable to GaN HEMTs on SiC substrates have been achieved. As a demonstration vehicle we designed and fabricated a GaN amplifier with pMOS gate bias control circuitry (a current mirror) and heterogeneous interconnects. This simple demonstration circuit is a building block for more advanced RF, mixed signal and power conditioning circuits, such as reconfigurable or linearized PAs with in-situ adaptive bias control, high power digital-to-analog converters (DACs), driver stages for on-wafer optoelectronics, and on-chip power distribution networks.

A 5-MHz IF digital FM demodulator

Key requirements for digital frequency-modulation (FM) demodulators are wide spurious-free dynamic range in the intermediate-frequency quantizer, linear-phase passband filtering, and accurate frequency discrimination. The proposed FM demodulator implemented digitally achieves high linearity by numerical differentiation performed at a 112/spl times/ oversampling rate, suppresses adjacent channels by placing zeros of the SINC function on them, and rejects amplitude-modulation (AM) components by numerical division. A 5-MHz FM demodulator integrated with a fourth-order bandpass delta-sigma front end exhibits 74.7 dB signal-to-noise ratio, -80.7 dB total harmonic distortion, and 61 dB AM rejection within a 9-kHz message bandwidth. The 0.65-/spl mu/m CMOS chip occupies 3.5/spl times/3.5 mm/sup 2/ of active area and consumes 180 mW with 4-V supply when clocked at 20 MHz.

A 1.7GHz 3V direct digital frequency synthesizer with an on-chip DAC in 0.35 /spl mu/m SiGe BiCMOS

A single-chip direct digital frequency synthesizer with hardware efficient phase-to-amplitude mapping and an integrated DAC achieves over 50dB SFDR in full-Nyquist band at 1.7GHz clock frequency for synthesized output signals up to 850MHz. The IC is implemented in a 0.35 /spl mu/m SiGe BiCMOS process and occupies an area of 4.8/spl times/5.0mm/sup 2/. Power efficiency is 1.76mW/MHz at 3V.

A 220-225.9 GHz InP HBT Single-Chip PLL

We present a 220 GHz fundamental PLL, based on a 220 GHz VCO, 2:1 dynamic frequency divider, fifth-order sub-harmonic phase detector, active loop filter, and output amplifier, fabricated in an InP HBT technology. The measured PLL locking range was 220.0 to 225.9 GHz, with -83 dBc/Hz of phase noise at a 100 KHz offset, while consuming 465.3 mW. The PLL occupies 1.1 mm2 including pads.

DC - 10GHz RF Digital to Analog Converter

Abstract- In this work we present recent results on high-speed, multi-Nyquist Digital-to-Analog Converter (DAC) capable of RF signal generation well above 10GHz. The DAC is implemented Teledynes InP double heterojunction bipolar transistor (DHBT) with 0.5im emitter width. The technology offers four level of gold interconnect with BCB dielectric, and thin-film resistor and MIM capacitor are available. Return-to-Zero (RZ) current switches are added to current steering DAC for high frequency wideband applications to achieve higher than 1GHz bandwidth. When clocked at 2.3GHz, the DAC output measures better than 60dB spurious-free dynamic range (SFDR) at 1GHz output frequency. With 2.7GHz data clock and 8.1GHz RZ clock, the measured performance is >50dBc SFDR at 8GHz output frequency. The chip measures 1450 x 2100im including bonding pads and dissipates 1.6 watt power.

A 1 V 6 b 50 MHz current-interpolating CMOS ADC

A current-interpolation technique is used to implement a 6 b 50 MHz ADC operable with a single battery cell as low as 0.9 V without charge pumping. The prototype chip, fabricated in a 0.35 /spl mu/m standard digital process, occupies an area of 2.4 mm/spl times/2 mm, and consumes 10 mW each in analog and digital supplies, respectively.

1-GS/s, 12-bit SiGe BiCMOS D/A converter for high-speed DDFs

This paper presents a 1-GS/s, 12-bit SiGe BiCMOS D/A converter combined with high-speed low-spurious BiCMOS current switches and an efficient calibration method for current mismatch. Experimental results show a reduction in INL and DNL errors from +35.5/-62.2 LSB to +4.1/-3.4 LSB and from +8.1/-10.3 LSB to +6.2/-1.2 LSB, respectively, after calibration. SFDR performance is 72.3 dBc at output frequency of 1.82 MHz and 50.0 dBc at output frequency of 334.39 MHz, when the sampling clock frequency is 1 GHz. Power consumption is about 950 mW at 100.48MHz output frequency and -3.3 V power supply.

Split accumulator with phase modulation for high speed low power direct digital synthesizers

A new split accumulator architecture to be used in direct digital frequency synthesizer (DDS) systems is presented in this paper. This new design takes into consideration that only part of the accumulator output is used to address the sine wave mapping. The most significant bits of the accumulator drive the mapping block and need to be updated on every sampling clock, while the least significant bits are not visible to the rest of the design and can be updated less frequently. Also the phase modulation adder is moved to the front of the accumulator. Benefits of the proposed architecture are fewer constraints in implementation, reduced power consumption of 40% (estimation) compared to standard approaches, and less area with no degradation in terms of spurious-free dynamic range (SFDR) performance.