N. Bheema Rao

EFFICIENT DELAY AND CROSSTALK ESTIMATION MODELS FOR CURRENT-MODE HIGH SPEED INTERCONNECTS UNDER RAMP INPUT

In this paper, closed-form models for the computation of finite ramp responses of current-mode resistance inductance capacitance (RLC) interconnects in VLSI circuits are presented. These models are based on extended Eudes model and Scaling and Squaring algorithm which allow numerical estimation of delay in lossy very large scale integration (VLSI) interconnects. The existing Eudes model for interconnect transfer function approximation is extended to higher-order and then Scaling and Squaring method is applied for further improving the accuracy of delay estimation. With the equivalent lossy interconnect transfer function, finite ramp responses are obtained and line delay is estimated for various line lengths, per unit inductances and load capacitances. The estimated 50% delay values are compared with HSPICE W-element model. The worst case errors observed in the estimated delay values are 14.3% for Eudes model and 2% for extended Eudes model while the proposed Scaling and Squaring based model with 1% error is in very good agreement with HSPICE for line lengths 0.1–0.5 cm. The estimated crosstalk induced delay values of proposed model maximum error percentage is nearly half of the extended Eudes model. For both single and three coupled interconnect lines, the proposed model is in good agreement with HSPICE.

Design of multi-layer fractal inductor for RF applications

Multilayered spiral inductor using fractal geometry is proposed. The proposed inductor achieves a high Q factor (Q) of 24.25 at a frequency of 19GHz with 43.5GHz as self resonant frequency (SRF). Design and EM simulations are performed by using high frequency structural simulator (HFSS) for 0.18μm TSMC technology. The results show 84.72% higher Quality factor than planar inductor with no negligible degradation in inductance value for over planar inductors. The results also show an 80% increase in SRF over planar inductor.

A novel fractal inductor for RF applications

In this paper, a novel fractal inductor was presented. This inductor provides a high quality factor of 19.8 at a frequency of 9.1GHz with SRF of 47.1 GHz. The simulations are carried out using Full wave High Frequency Structural Simulator (HFSS) for a single layered 0.18μm technology. The simulation results show an improvement in quality factor by 22% over conventional fractal inductor and results also shows an improvement in SRF by 21% over conventional fractal inductor.

C-based predictor for scoreboard in Universal Verification Methodology

Universal Verification Methodology (UVM) is a standardized hybrid methodology for verifying complex integrated circuit designs in the semiconductor industry. Predictor is a component in UVM based test bench that represents a golden model of the design under test (DUT), which generates an expected response against which the actual response of the DUT is compared in scoreboard. Predictors are mostly written in C or C++ for modelling the correct functionality of the DUT. It is provided in the form of compiled object code to the testbench and acts as a verification component. UVM uses SystemVerilog Direct Programming Interface (DPI) for communicating components written in C with other components of the test bench. This paper describes implementation of a UVM testbench consisting of a C based predictor, in the form of a complied object code for verification of a fused floating-point add-subtract design unit.

A closed-form delay estimation model for current-mode high speed VLSI interconnects

Closed-form model for the delay estimation of current-mode Resistance Inductance Capacitance (RLC) interconnects in VLSI circuits is presented. The existing Eudes model for interconnect transfer function approximation is extended and applied for further accurate estimation of delay. With the equivalent lossy interconnect transfer function, finite ramp responses are obtained and line delay is estimated for various line lengths, per unit length inductances and load capacitances. The delay values are computed using Eudes model, extended Eudes model and are compared with the HSPICE W-element model. The obtained delay values of existing Eudes model max error percentage is 14.3% whereas our extended Eudes model is in good agreement with those of HSPICE results within 2% for the line lengths of 1mm to 10mm.

An efficient delay estimation model for high speed VLSI interconnects

In this paper a closed-form matrix rational model for the computation of step and finite ramp responses of Resistance Inductance Capacitance (RLC) interconnects in VLSI circuits is presented. This model allows the numerical estimation of delay and overshoot in lossy VLSI interconnects. The proposed method is based on the U-transform, which provides rational function approximation for obtaining passive interconnect model. With the reduced order lossy interconnect transfer function, step and finite ramp responses are obtained and line delay and signal overshoot are estimated. The estimated delay and overshoot values are compared with the Eudes method, Pade method and HSPICE W- element model. The 50% delay results are in good agreement with those of HSPICE within 0.5% error while the overshoot error is within 1% for a 2 mm long interconnect. For global lines of length more than 5 mm in SOC (system on chip) applications, the proposed method is found to be nearly four times more accurate than existing methods.

A Novel Fractal Stacked Inductor Using Modified Hilbert Space Filling Curve for RFICs

High quality factor miniaturized inductors are prerequisites of RFIC applications. This paper presents a novel fractal stacked inductors using modified Hilbert space filling curve. The proposed inductor is constructed in series stack fashion according to the process rules to achieve higher inductance values. Using the modified Hilbert structure, lateral flux is eliminated to achieve higher Q values. The results show that more than 90% improvement in L over conventional fractal inductor within same occupying area and more than 10% improvement in Q factor over standard stacked inductor.

Fractal spiral capacitor for RF applications

A novel single layered fractal spiral capacitor has been designed using fractal geometry. The simulation results carried out by High Frequency Structural Simulator. The simulation results shows fractal spiral capacitor provides10.3% improvement in Capacitance, 52.4% improvement in Q factor and 20% improvement in self resonant frequency over standard spiral capacitor.

Design of multilayer on-chip inductor with low k-dielectrics for RF applications

In this paper the effect of low k dielectrics on Quality factor is studied using multi level interconnect technology. With low-K dielectric we achieved improvement in the Quality factor of spiral inductor at higher frequency. From the simulation results the proposed inductor using low k dielectric achieved high Q with 100% improvement when compared with basic CMOS process on chip inductor. The percentage of increase in quality will improve as we increase the outer diameter of the spiral inductor. It is also observed the effect of conductor width and outer diameter on the proposed inductor following standard rules defined. The proposed inductor structure occupies maximum area of 20μm×20μm which is suitable for higher order RF frequency applications.

Multilayer grown high-Q on-chip inductor for RF applications

In this paper a multi-layer grown spiral inductor is presented with higher Quality factor by 72% and self resonance frequency (SRF) by 17%, over planar spiral inductors for RF applications at 3.65 GHz. Higher Quality factor of multi layer inductor over planar inductor is obtained at higher order frequencies for smaller outer diameters by taking substrate loss into consideration. There is no significant change in inductance for both the inductors. The area of cross-section for the proposed inductor is 420μm×420μm. Proposed Multi layer inductor is designed on silicon substrate and shape of conductor is considered as rectangular for simple and accurate analysis. Proposed inductor is designed and simulated in HFSS V12 for obtaining Quality factor and Inductance. Proposed inductor can be performed up to GHz frequency range and is efficiently suitable for Microwave/RF and wireless communication applications.