N. Cartiglia

Temperature effects on radiation damage to silicon detectors

Abstract Motivated by the large particle fluences anticipated for the SSC and LHC, we are performing a systematic study of radiation damage to silicon microstrip detectors. Here we report radiation effects on detectors cooled to 0°C (the proposed operating point for a large SSC silicon tracker) including leakage currents and change in depletion voltage. We also present results on the annealing behavior of the radiation damage. Finally, we report results of charge collection measurements of the damaged detectors made with an 241 Am α source.

Temperature dependence of radiation damage and its annealing in silicon detectors

Silicon detectors at future collider facilities such as the Superconducting Super Collider (SSC) will be exposed to large fluences of both neutral and charged particles, resulting in considerable bulk radiation damage. In order to reduce the increase in leakage current associated with that damage, the proposed operating temperature of the silicon detectors in the SSC Solenoidal Detector Collaboration (SDC) experiment is 0 degrees C. In order to explore any potential complications of operating detectors at 0 degrees C, two sets of detectors were irradiated. One set was kept close to 0 degrees C during the exposure and annealing period, while the other was maintained at room temperature throughout ( approximately 27 degrees C during the exposure, and approximately 23 degrees C during the annealing period). The full depletion voltage and leakage current of the detectors during the irradiation period and over the subsequent annealing period were monitored. It is concluded that detectors will have to be operated at 0 degrees C, and, once damaged, be maintained at 0 degrees C in order to keep their operating voltage at a reasonable value ( >

Double-sided microstrip sensor for the barrel of the SDC silicon tracker

Abstract A full-size prototype microstrip sensor for the silicon tracker of the SDC detector to be used at the Superconducting Super Collider has been fabricated at Hamamatsu Photonics. The sensor is double-sided, using an AC-coupled readout with 50 μm pitch strips. The sensor size is 3.4 × 6.0 cm 2 . Polycrystalline silicon is used as a bias feeding resistor on both surfaces. Each ohmic strip is isolated by a p + blocking line. The detailed requirements for the silicon tracker and the corresponding specifications as well as how to achieve them are discussed. The static performances of this prototype sensor are presented.

Tests of the radiation hardness of VLSI integrated circuits and silicon strip detectors for the SSC under neutron, proton, and gamma irradiation

As part of a program to develop a silicon strip central tracking detector system for the Superconducting Super Collider (SSC), the effects of radiation damage in silicon detectors and their associated front-end readout electronics are being studied. The authors report on the results of neutron and proton irradiations at the Los Alamos National Laboratory and gamma -ray irradiations at UC Santa Cruz. Individual components on single-sided AC-coupled silicon strip detectors and on test structures were tested. Circuits fabricated in a radiation-hard CMOS process and individual transistors fabricated using dielectric isolation bipolar technology were also studied. Bulk damage to the silicon itself is seen as the limiting factor in the lifetime of a detector system. In particular, it is the acceptor site creation in the active volume of the silicon detector that will limit the lifetime to approximately 10 yr for the innermost detectors. >

Measurement of proton induced radiation damage to CMOS transistors and p-i-n diodes

As part of a program to develop a silicon tracking device for the Superconducting Super Collider (SSC), radiation-hard CMOS transistors and p-i-n diodes have been exposed to the 800-MeV LAMPF (Los Alamos Meson Physics Facility) proton beam. The fluences accumulated in one week corresponded to the expected radiation levels of about ten SSC years. The leakage current constants for p-i-n diodes and threshold voltage shifts for CMOS transistors are determined under different biasing conditions. The results are presented and examined in detail. >

A low power bipolar amplifier integrated circuit for the ZEUS silicon strip system

Abstract A fast low power bipolar chip consisting of 64 amplifier-comparators has been developed for use with silicon strip detectors for systems where high radiation levels and high occupancy considerations are important. The design is described and test results are presented.

A fast shaping amplifier-comparator integrated circuit for silicon strip detectors

A 64-channel amplifier-comparator silicon strip detector fabricated on the Tekronix SHPi bipolar process is described. This device is particularly useful in high rate colliders with silicon strip vertex detection. This amplifier-comparator meets the performance goals for the ZEUS LPS. It has low noise, radiation resistance, very low power, and good stability, and is easy to use. The power use and noise are close to those needed in the SDC tracker for the SSC (Superconducting Super Collider). Circuit measurements show that the circuit will perform properly in its expected environment.<<ETX>>

Analysis of capacitance measurements on silicon microstrip detectors

We present an analysis of the total strip capacitance of double-sided, AC-coupled silicon microstrip detectors. We evaluate the radiation hardness and the noise contribution of different strip geometries. We comment on a serious failure mode. >

Testing and installation of ZEUS Leading Proton Spectrometer detector planes

Abstract The assembly and testing of the components which make up a detector plane for the Leading Proton Spectrometer is described. The spectrometer, a part of the ZEUS detector, utilizes single-sided DC-coupled silicon strip detectors and custom VLSI front-end electronics for readout.

Measurement of interstrip and coupling capacitances of silicon microstrip detectors

The authors present a set of measurements of the capacitances on silicon microstrip detectors which are important for the operation of the detectors. Various strip widths on both the junction and the ohmic side and widths of blocking p+ implant on the ohmic side have been implemented on test detectors. The interstrip, body, and coupling capacitances of the strips were frequency dependent. SPICE was used to simulate the resistive and capacitive network represented by the detectors, and good agreement between measurement and simulation was found. The detectors were irradiated with ionizing radiation to test the radiation hardness of the design. The noise increase induced in a fast low-noise amplifier due to the capacitive load of different strip geometries was measured. The results agree with those obtained using discrete external capacitors.<<ETX>>