N. Horiguchi

The economic impact of EUV lithography on critical process modules

Traditionally, semiconductor density scaling has been supported by optical lithography. The ability of the exposure tools to provide shorter exposure wavelengths or higher numerical apertures have allowed optical lithography be on the forefront of dimensional scaling for the semiconductor industry. Unfortunately, the roadmap for lithography is currently at a juncture of a major paradigm shift. EUV Lithography is steadily maturing but not fully ready to be inserted into HVM. Unfortunately, there are no alternative litho candidates on the horizon that can take over from 193nm. As a result, it is important to look into the insertion point of EUV that would be ideal for the industry from an economical perspective. This paper details the benefit observed by such a transition. Furthermore, it looks into such detail with an EUV throughput sensitivity study.

Design Technology co-optimization for N10

Design-Technology co-optimization becomes a key knob to enable CMOS scaling. In this work we evaluate the technology options including lithography options as well as device options that are considered to enable N10 scaling by exploring their impact on representative designs such as standard cells, SRAM and analog contexts. This paper illustrates that the design angle needs to be considered early in the development of a technology node. This design assessment and decisions start from lithography constraints and options to power/performance, area and cost, all of which create the Design-Technology Co-Optimization space.

3D-carrier profiling in FinFETs using scanning spreading resistance microscopy

In this work, we demonstrate for the first time 3D-carrier profiling in FinFETs with nm-spatial resolution using SSRM. The results provide information on gate underlap, dopant conformality, source/drain doping profiles. The 3D-carrier profiles as extracted for two different device approaches (extensions vs. extension-less) are conclusive in demonstrating the differences in device performance and are consistent with first order 3D-simulations.

Phosphorus doped SiC Source Drain and SiGe channel for scaled bulk FinFETs

A P-SiC (Phosphorus doped Si1-xCx) SD (Source Drain) was developed on bulk-Si based nMOS FinFETs (n-FinFETs). P-SiC epitaxial growth on SD provides strain to boost n-FinFET mobility and drive current. Combination of LA (Laser Anneal) and low temperature RTA recovers P-SiC and PSi (Phosphorus doped Si, Si1-xPx) strain. A SiGe clad channel on pMOS FinFETs (p-FinFETs) was investigated. Narrower Si fin and SiGe epitaxial growth on fins increase mobility and drive current, which is based on the same carrier transport mechanism as conventional phonon scattering without velocity overshoot around 14nm node.

The need for EUV lithography at advanced technology for sustainable wafer cost

Extreme Ultra-Violet lithography (EUVL) is considered as the most promising candidate to replace optical lithography from the 14nm technology node onwards. EUVL has recently been supplanted by multiple patterning using existing 193nm immersion lithography tools for upcoming 14 nm technology node due to the current resolution limitations and production level efficiency restrictions. In this paper, a wafer cost model for technology node from 28nm down to 14nm has been developed. It identifies lithography module as the key component where innovation can be leveraged to reduce cost. The results presented in the paper reveal that wafer cost will be increased by 30% from 28nm to 20nm technology node. A 70% increase in wafer cost is foreseen during a transition from 20nm to 14nm node based on 193nm immersion lithography and multiple patterning. The cost analysis predicts a 30% wafer cost reduction by adapting EUVL at a 14 nm technology node compared to 193nm immersion technology (normalized to 28nm wafer cost). It proves that the readiness of EUVL is critical to keep scale the logic devices at the pace of Moore’s law without violating the scale of economics in semiconductor industry.

Study of (correlated) trap sites in SILC, BTI and RTN in SiON and HKMG devices

Recently, several experimental groups have found correlations in gate and drain current fluctuations. In this paper, by studying single trap activated leakage paths, both evidence and a refined 4-state defect model are provided, ascribing additional gate tunneling current in nm-FETs to thermally activated defect states. The model is capable of explaining both positive and negative correlations in gate and drain current RTN, but also the mostly uncorrelated nature of these drain and gate RTN signals.

Integration of III-V on Si for High-Mobility CMOS

In this paper we present results from an InGaAs/InP implant free quantum well device integrated fully in a Si CMOS processing line. The virtual InP substrates are generated using a Si template which is prepared by standard STI processing. The Si in the STI trenches is etched and a Ge seed layer grown.

Patterning challenges in advanced device architectures: FinFETs to nanowires

Si FinFET scaling is getting more difficult due to extremely narrow fin width control and power dissipation. Nanowire FETs and high mobility channel are attractive options for CMOS scaling. Nanowire FETs can maintain good electrostatics with relaxed nanowire diameter. High mobility channel can provide good performance at low power operation. However their fin patterning is challenging due to fins consisted of different materials or fragile high mobility material. Controlled etch and strip are necessary for good fin cd and profile control. Fin height increase is a general trend of scaled FinFETs and nanowire FETs, which makes patterning difficult not only in fin, but also in gate, spacer and replacement metal gate. It is important that gate and spacer etch have high selectivity to fins and good cd and profile control even with high aspect ratio of fin and gate. Work function metal gate patterning in scaled replacement metal gate module needs controlled isotropic etch without damaging gate dielectric. SF6 based etch provides sharp N-P boundary and improved gate reliability.

Electrical Characteristics of p-Type Bulk Si Fin Field-Effect Transistor Using Solid-Source Doping With 1-nm Phosphosilicate Glass

For scaling of bulk Si Fin field-effect transistor (FinFET), suppression of short-channel effects is required without ON-state current degradation. In this letter, solid-source doping for channel doping using 1-nm phosphosilicate glass was demonstrated on both p-type (100) Si substrate and p-type bulk Si FinFET. The profile of phosphorus in p-type (100) Si substrate was analyzed by secondary ion mass spectrometry and it was diffused deeper with higher thermal budget of anneal. Fabricated bulk Si FinFETs with using 1-nm phosphosilicate glass showed threshold voltage shift with several anneals at 1-μm and 70-nm gate lengths. Hole mobility at 1-μm gate length and transconductance at 70-nm gate length were also reduced due to increase in impurity concentration of phosphorus diffused by anneals into Fins. Phosphorus diffusion into Fins with using 1-nm phosphosilicate glass was investigated and phosphorus behavior after anneal was clarified by electrical data of p-type bulk Si FinFETs.

A new high-k/metal gate CMOS integration scheme (Diffusion and Gate Replacement) suppressing gate height asymmetry and compatible with high-thermal budget memory technologies

A new scheme called in the following “Diffusion and Gate Replacement” (D&GR) MIPS integration is demonstrated. The CMOS flow allows to control the gate height asymmetry between NMOS and PMOS by driving the work function shifter directly into the high-k. Since the threshold voltage (Vth) shifter sources are removed, it is compatible with other processes requiring high-thermal budget such as memory technologies (DRAM periphery).