N. N. Levchenko

Debugging and testing features of the dataflow parallel computing system components and devices

The paper describes the new tools for dynamic display of the computational process for modeling a dataflow parallel computing system that implements non-traditional architecture. These tools allow evaluating the effectiveness of program and localization functions during the task.

Approaches to the development of various sets of nodes and blocks for the PDCS matching processor

This article describes approaches to building a set of nodes and blocks that are sufficient to create the matching processor for the parallel dataflow computing system. Investigations of various sets of nodes and blocks of the matching processor have been carried out. As a result, some regularities were revealed characteristic for hardware-software solutions that implement the dataflow computing model. The approaches to composing the matching processor are presented. The research data will be used to create special computers for a specific range of tasks.

Dataflow computing model — Perspectives, advantages and implementation

The problems of parallelizing computations and increasing real performance are among the main ones for high-performance computing systems. The article describes a new dataflow computing model and architecture, which allow addressing these problems. Methods for solving other problems of classical dataflow systems and traditional cluster supercomputers by the parallel dataflow computing system are also presented. The experiment results for one of the task are shown. It is concluded that the new dataflow computing model is promising.

The current state of evolution of content addressable memory architecture and aspects of its usage in the PDCS “Buran”

The article provides an overview of the main directions of the development of architectures of content addressable memory and associative processors. The main problems that are facing the developers of these devices are identified. The description of the content addressable memory of keys in the matching processor, which is the main computation process control device in the parallel dataflow computing system (PDCS) “Buran”, is given. Existing methods to increase the speed and reduce power consumption for various types of content addressable memory (CAM, TCAM, etc.) are considered. Various TCAM architectures implemented on the nonvolatile memory technology, as well as associative processors are described.

Investigation of sparse matrix multiplication task for the PDCS “Buran”

In order to improve the efficiency of the sparse matrices multiplication task on a traditional cluster supercomputer, it is necessary to take into account different levels of parallelism when programming. To work around these problems the dataflow computing model with the dynamically formed context and the architecture of the parallel dataflow computing system can be used. The article describes the implementation of a parallel algorithm of the sparse matrices multiplication task on the parallel dataflow computing system. The experiments performed on the emulator of the system demonstrate the application perspectiveness of the dataflow computing model for this class of tasks.

The PDCS “Buran” operating efficiency improvement ways

This paper outlines the architecture of parallel dataflow computing system and its general parameters, which could be modified to improve the operating efficiency of the system for one or another class of problems. Distribution functions allow to improve operating efficiency of the system due to scalability improvement of the task (paralleling on a greater number of computational cores). Other adaptation methods of the computing system for various tasks are given.

I/O processor as the device for computing process management in the PDCS “Buran”

The paper presents the main differences of the new computing model and the system that implements this model from traditional dataflow systems. The parallel dataflow computing system architecture and I/O processor are briefly described. I/O processor is one of the main management elements of computing process in the system. Functionality of the token-generating unit and various input-output modes are also described. The data obtained with some experiments, which were carried out at the modelling programme for a number of problems, are given.

Development tools for high-performance computing systems using associative environment for computing process organization

The paper presents the development tools for parallel dataflow computing systems that use associative environment for computing process organization. Such tools are organized as the Software complex for dataflow systems development. They allow to assess the operating efficiency of various associative environment implementation variants. They also allow to evaluate the execution efficiency of tasks from different knowledge areas, to evaluate the programs scalability level on a variety of computing systems configurations and to select a computation distribution functions for localization of computations in time and space.

Research of asynchronous algorithm for molecular dynamics task on the PDCS “Buran” models

Molecular dynamics (MD) task scales poorly due to the global barriers used to maintain neighbour lists. The paper presents the asynchronous algorithm for MD task simulation free from this drawback. The experiments with MD on various models of parallel dataflow computing system (PDCS) “Buran ” also presented. Synchronization in this algorithm relies solely on the local interactions between the cores responsible for nearby areas. The paper describes a series of experiments with MD task on cycle-accurate and behaviour block-register models as well as on PDCS emulator (on cluster) which allow to re-assessing capabilities of the created computing system. Scalability for the tasks with equal size on PDCS will be by one-two orders higher than on the traditional systems. Furthermore, the research has shown the possibility to create the simple version of basic algorithm, from which can be derived the more efficient completely asynchronous algorithm based on counting of the transmitted particles.

Decreasing the power consumption of content-addressable memory in the dataflow parallel computing system

This article proposes the way to decrease the power consumption of content-addressable memory in dataflow parallel computing system. The proposed method is to split a memory word into several short segments and start the searching in the each successive segment only if there is match in the previous one. This approach allows decreasing the number of bit search operations by 77% according to software modeling results.