N. Novkovski

Constant current stress of Ti-doped Ta2O5 on nitrided Si

The response of Ti-doped Ta2O5 stacked films (4‐6nm) to constant current stress (CCS) under gate injection has been investigated. Two doping methods (‘surface’ and ‘bulk’ doping of Ta2O5) as well as two Si-surface nitridation processes (rapid thermal annealing in N2O and NH3) have been used to prepare the stacks. The effect of doping approach, Si-surface nitridation and the metal electrode (Al and W) on the dielectric degradation has been discussed in terms of stress-induced leakage current (SILC), stress-induced flat band voltage shifts, charge trapping and defect generation. CCS generates charges in the bulk dielectric and in slow states, whose sign and amount depend on both the nitridation process and the doping approach. The method of doping has the strongest impact on the SILC whose behaviour is found to be substantially different from that in SiO2. The method of doping plays a crucial role in the CCS degradation and can be used as an enabling tool for control of this degradation. The gate-deposition-induced defects are another key factor which controls the stress degradation. These defects are very susceptible to electrical stress and could lead to serious reliability concerns. (Some figures in this article are in colour only in the electronic version)

Effects of the metal gate on the stress-induced traps in Ta2O5/SiO2 stacks

Abstract The degradation of Ta2O5-based (10xa0nm) stacked capacitors with different top electrodes, (Al, W, Au) under constant current stress has been investigated. The variation of electrical characteristics after the stress is addressed to gate-induced defects rather than to poor-oxidation related defects. The main wearout parameter in Ta2O5 stacks is bulk-related and a generation only of bulk traps giving rise to oxide charge is observed. The post-stress current–voltage curves reveal that stress-induced leakage current (SILC) mode occurs in all capacitors and the characteristics of pre-existing traps define the stress response. The results are discussed in terms of simultaneous action of two competing processes: negative charge trapping in pre-existing electron traps and stress-induced positive charge generation, and the domination of one of them in dependence on both the stress level and the gate used. The charge build-up and the trapping/detrapping processes modify the dominant conduction mechanism and the gate-induced defects are precursors for device degradation. It is concluded that the impact of the metal gate on the ultimate reliability of high-k stacked capacitors should be strongly considered.

Charge trapping effect at the contact between a high-work-function metal and Ta2O5 high-k dielectric

Metal(Al,W,Au)–dielectric(tantalum oxide)–Si structures were studied at constant low current injection (J = 0.025–0.1 mA cm−2). It was found that in the case of an Au electrode the voltage required to maintain a constant current increases with the injection time up to a saturated value. The process is reversible, as was confirmed by repeating the injection after a 58 h long pause. The observed effect is attributed to discharging into the metal conduction band of the near interface traps with energy levels higher than the Au Fermi level at zero voltage and charging with electrons injected into the insulator during current injection. The traps are attributed to the cap type vacancies near the interface being more stable when positively charged in the case of a high-work-function metal, as previously found by Ramprasad by first principle total energy calculations.

Temperature dependence of leakage currents in Ti-doped Ta2O5 films on nitrided silicon

Conduction mechanisms and electrically active defects in rf sputtered Ti doped Ta2O5 thin films have been investigated by analysing the impact of temperature on the I–V curves. The films (about 6 nm thick) were grown on silicon substrates nitrided in N2O or NH3 ambient. Two different methods of Ti incorporation were used—a surface doping, where a thin Ti layer is deposited on the top of Ta2O5, and a bulk doping, where the Ti layer is sandwiched between two layers of Ta2O5. The I–V characteristics were measured in a temperature range from 30 to 100 °C. Current is found to be governed mainly by the modified Poole–Frenkel (PF) effect, with a temperature dependent degree of compensation. Two types of trap centres involved in the PF conduction process have been identified: shallow traps located at about 0.3–0.4 eV below the conduction band edge of the dielectric, present in all doped films, and deeper centres at 0.65 eV, present only in the bulk-doped films. The origin of these trap centres is also discussed.

Constant current stress-induced leakage current in mixed HfO2–Ta2O5 stacks

Abstract The electrical characteristics of HfO2–Ta2O5 mixed stacks under constant current stress (CCS) at gate injection with 20xa0mA/cm2 and stressing times of 50 and 200xa0s have been investigated. A very weak effect of the stress on the global dielectric constant, on fast and slow states in the stack as well as on the dominant conduction mechanism is detected. The most sensitive parameter to the CCS is the leakage current. The stress-induced leakage current (SILC) is voltage and thickness dependent. The pre-existing traps govern the trapping kinetics and are a key parameter to evaluate the stress response. Two processes – positive charge build-up and new bulk traps generation – are suggested to be responsible for SILC: the domination of one of them depends on both the film thickness and the stressing time. The positive charge build-up is localized close to the gate electrode implying gate-induced defects could be precursors for it. It is established that unlike the case of single SiO2 layer, the bulk traps closer to the gate electrode control SILC in the mixed Ta2O5–HfO2-based capacitors.

Electrical properties of thin RF sputtered Ta2O5 films after constant current stress

Abstract Stress-induced leakage currents (SILCs) in thin Ta2O5 films after short- and long-term constant current stress (CCS) at both gate polarities at different levels of injected current were investigated. The behavior of the SILCs and the change of quasistatic C–V characteristics after the degradation confirmed the variations of gate voltage with time during CCS necessary to maintain the injected current density through the oxide. The conduction mechanisms were also investigated. Initially, normal Poole–Frenkel (PF) mechanism dominates in the oxide at medium fields (0.4– 1.7 MV/cm) independently of the deposition temperature or annealing steps. After the degradation modified PF with different compensation factors appears. After long-term degradation conduction mechanism goes back to PF.

Time-dependent-dielectric-breakdown characteristics of Hf-doped Ta2O5/SiO2 stack

Abstract The Time-Dependent-Dielectric Breakdown (TDDB) characteristics of MOS capacitors with Hf-doped Ta 2 O 5 films (8xa0nm) have been analyzed. The devices were investigated by applying a constant voltage stress at gate injection, at room and elevated temperatures. Stress voltage and temperature dependences of hard breakdown of undoped and Hf-doped Ta 2 O 5 were compared. The doped Ta 2 O 5 exhibits improved TDDB characteristics in regard to the pure one. The maximum voltage projected for a 10xa0years lifetime at room temperature is −2.4xa0V. The presence of Hf into the matrix of Ta 2 O 5 modifies the dielectric breakdown mechanism making it more adequate to the percolation model. The peculiarities of Weibull distribution of dielectric breakdown are discussed in terms of effect of three factors: nature of pre-existing traps and trapping phenomena; stress-induced new traps generation; interface layer degradation.

Effect of Al gate on the electrical behaviour of Al-doped Ta2O5 stacks

The electrical behaviour of Al-doped Ta2O5 films on nitrided silicon and implemented in Al-gated MIS capacitors has been studied. The dopant was introduced into the Ta2O5 through its surface by deposing a thin Al layer on the top of Ta2O5 followed by an annealing process. The HRTEM images reveal that the initial double-layer structure of the stacks composed of doped Ta2O5 and interfacial SiON layer undergoes changes during the formation of the Al gate and transforms into a three-layer structure with an additional layer between the Al electrode and the doped Ta2O5. This layer, being a result of reaction between the Al gate and the Al-doped Ta2O5, affects the overall electrical properties of the stacks. Strong charge trapping/detrapping processes have been established in the vicinity of the doped Ta2O5/SiON interface resulting in a large C–V hysteresis effect. The charge trapping also influences the current conduction in the layers keeping the current density level rather low even at high electric fields (J < 10−6 A cm−2 at 7 MV cm−1). By employing a three-layer model of the stack, the permittivity of both, the Al-doped Ta2O5 and the additional layer, has been estimated and the corresponding conduction mechanisms identified.

Density and spatial distribution of MERIE‐like plasma induced defects in SiO2

Generation of electrically active defects by Magnetron Enhanced Reactive Ion Etching (MERIE)-like He plasma in thin (12 nm) SiO2–Si structures is investigated by C–V and I–V techniques. It is found that the plasma creates positive charge near the Si–SiO2 interface and negative one near the Al–SiO2 interface, both with significant density (>1012 cm−2). The centroid and the density of the negative oxide charge depend strongly on plasma conditions and location of wafers during the plasma exposure. It is established that the negative charge generated behaves as “fixed” oxide charge and cannot be charged or discharged. The trapping properties of the plasma damaged structures are studied by a constant current stress. The density of the trapped charge is generally small and its sign depends on the level of injection current. (© 2003 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Analysis of Conduction and Charging Mechanisms in Atomic Layer Deposited Multilayered HfO2/Al2O3 Stacks for Use in Charge Trapping Flash Memories

Method for characterization of electrical and trapping properties of multilayered high permittivity stacks for use in charge trapping flash memories is proposed. Application of the method to the case of multilayered HfO2/Al2O3 stacks is presented. By applying our previously developed comprehensive model for MOS structures containing high- dielectrics on the characteristics measured in the voltage range without marked degradation and charge trapping (from −3u2009V to +3u2009V), several parameters of the structure connected to the interfacial layer and the conduction mechanisms have been extracted. We found that the above analysis gives precise information on the main characteristics and the quality of the injection layer. characteristics of stressed (with write and erase pulses) structures recorded in a limited range of voltages between −1u2009V and +1u2009V (where neither significant charge trapping nor visible degradation of the structures is expected to occur) were used in order to provide measures of the effect of stresses with no influence of the measurement process. Both trapped charge and the distribution of interface states have been determined using modified Terman method for fresh structures and for structures stressed with write and erase cycles. The proposed method allows determination of charge trapping and interface state with high resolution, promising a precise characterization of multilayered high permittivity stacks for use in charge trapping flash memories.