N. Zorzi

Characterization of the First Prototypes of Silicon Photomultiplier Fabricated at ITC-irst

This paper reports on the electrical characterization of the first prototypes of Geiger-Mode Avalanche Photodiodes (GM-APDs) and Silicon Photomultipliers (SiPMs) produced at ITC-irst, Trento. Both static and functional measurements have been performed in dark condition. The static tests, consisting in reverse and forward IV measurements, have been performed on 20GM-APDs and 90 SiPMs. The breakdown voltage, the quenching resistance value and the current level have been proved to be very uniform. On the other hand, the analysis of the dark signals allowed the extraction of important properties such as the dark count rate, the gain, the after-pulse and optical cross-talk (in case of the SiPMs) rates. These parameters have been evaluated as a function of the bias voltage, showing trends perfectly compatible with the theory of the device

Recent developments on silicon photomultipliers produced at FBK-irst

In this contribution, new developments on the silicon photomultipliers (SiPMs) fabricated at FBK-irst (Trento, Italy) are reported. With respect to the first series of devices produced in 2005/2006, there have been major improvements on both the the layout and the technology. Concerning the first aspect we fabricated SiPMs with increased fill factor and with different geometries (square/circular devices, arrays and matrices of SiPMs) to meet the requirements of different applications. Concerning the technology, we identified a process technique able to reduce significantly the dark count rate. In this paper we will describe the main electro-optical characteristics of these devices.

Development of a fabrication technology for double-sided AC-coupled silicon microstrip detectors

Abstract We report on the development of a fabrication technology for double-sided, AC-coupled silicon microstrip detectors for tracking applications. Two batches of detectors with good electrical figures and a low defect rate were successfully manufactured at IRST Laboratory. The processing techniques and the experimental results obtained from these detector prototypes are presented and discussed.

Test beam results of 3D silicon pixel sensors for the ATLAS upgrade

Results on beam tests of 3D silicon pixel sensors aimed at the ATLAS Insertable B-Layer and High Luminosity LHC (HL-LHC) upgrades are presented. Measurements include charge collection, tracking efficiency and charge sharing between pixel cells, as a function of track incident angle, and were performed with and without a 1.6 T magnetic field oriented as the ATLAS inner detector solenoid field. Sensors were bump-bonded to the front-end chip currently used in the ATLAS pixel detector. Full 3D sensors, with electrodes penetrating through the entire wafer thickness and active edge, and double-sided 3D sensors with partially overlapping bias and read-out electrodes were tested and showed comparable performance.

A fabrication process for silicon microstrip detectors with integrated front-end electronics

We report on an research and development activity aimed at the fabrication of silicon microstrip detectors with integrated front-end electronics to be used in high-energy physics and space experiments and medical/industrial imaging applications. A specially tailored fabrication technology has been developed at ITC-IRST (Trento, Italy), which allows for the production of single-sided microstrip detectors, with integrated coupling capacitors and polysilicon resistors, as well as active devices, including N-channel junction field effect transistors and N- or P-channel MOS transistors. The main characteristics of the fabrication process are outlined. Experimental results from the electrical characterization of the devices are reported, showing that transistors with good electrical figures can be obtained within the proposed technology while preserving the basic detector parameters.

Test structure for mismatch characterization of MOS transistors in subthreshold regime

This paper proposes a simple test circuit for characterization of MOS transistor mismatch in a standard 2 /spl mu/m CMOS technology. Measurements have been performed both in the saturation and subthreshold regimes in order to obtain an accurate characterization in a wide range of operations. The parameter mismatch estimation algorithm is based on Multiple Linear Regression and is able to furnish information on the estimation accuracy.

Feasibility studies of microelectrode silicon detectors with integrated electronics

Abstract We describe our experience on design and fabrication, on high-resistivity silicon substrates, of microstrip detectors and integrated electronics, devoted to high-energy physics experiments and medical/industrial imaging applications. We report on the full program of our collaboration, with particular regards to the tuning of a new fabrication process, allowing for the production of good quality transistors, while keeping under control the basic detector parameters, such as leakage current. Experimental results on JFET and bipolar transistors are presented, and a microstrip detector with an integrated JFET in source–follower configuration is introduced.

New results on the characterization of ITC-irst Silicon Photomultipliers

In this paper we report briefly on the development of Silicon Photomultipliers at ITC-irst. First, details on the technology and geometry are given. Then, experimental data are shown including static IV characterization, signal characterization, noise properties and photodetection efficiency.

Radiation hardness and charge collection efficiency of lithium irradiated thin silicon diodes

Due to their low depletion voltage, even after high particle fluences, improved tracking precision and momentum resolution, and reduced material budget, thin substrates are one of the possible choices to provide radiation hard detectors for future high energy physics experiments. In the framework of the CERN RD50 Collaboration, we have developed PIN diode detectors on membranes obtained by locally thinning the silicon substrate by means of TMAH etching from the wafer backside. Diodes of different shapes and sizes have been fabricated on 50-/spl mu/m and 100-/spl mu/m thick membranes and tested, showing a low leakage current (of 300 nA/cm/sup 3/) and a very low depletion voltage (in the order of 1 V for the 50 /spl mu/m membrane) before irradiation. Radiation damage tests have been performed with 58 MeV lithium (Li) ions up to the fluence of 10/sup 14/ Li/cm/sup 2/ in order to determine the depletion voltage and leakage current density increase after irradiation. Charge collection efficiency tests carried out with a /spl beta//sup -/ particle source have been performed on both nonirradiated devices and samples irradiated up to 1.8/spl times/10/sup 13/ Li/cm/sup 2/. Results reported here confirm the advantages of thinned diodes with respect to standard 300-/spl mu/m thick devices in terms of low depletion voltage and high charge collection efficiency.

Design and characterization of integrated front-end transistors in a micro-strip detector technology

Abstract We present the developments in a research program aimed at the realization of silicon micro-strip detectors with front-end electronics integrated in a high resistivity substrate to be used in high-energy physics, space and medical/industrial imaging applications. We report on the fabrication process developed at IRST (Trento, Italy), the characterization of the basic wafer parameters and measurements of the relevant working characteristics of the integrated transistors and related test structures.