Nabeeh Kandalaft

Testing 3-D IC Through-Silicon-Vias (TSVs) by Direct Probing

Testing the integrity of interconnects realized by through silicon vias (TSVs) in 3-D integrated circuits (3-D IC) is considered a challenging task. TSVs are excessively small and fragile for current probe technology. In this paper, a new spring-type probe using microelectromechanical systems (MEMS) technology is presented. The implemented MEMS probe supports the required pitch for TSV direct probing and minimizes the undesired scrub marks on TSV surface. Simulation results indicate that the implemented MEMS probe can operate at the gigahertz frequency range without significant test signal degradation.

Low-Contact Resistance Probe Card Using MEMS Technology

Multichannel die probing increases test speed and lowers the overall cost of testing. A new high-density wafer probe card based on MEMS technology is presented in this paper. MEMS-based microtest-channels have been designed to establish high-speed low-resistance connectivity between the die-under-test and the tester at the wafer level. The proposed test scheme can be used to probe fine pitch pads and interconnects of a new generation of 3-D integrated circuits. The proposed MEMS probe, which is fabricated with two masks, supports \(10^{6}\) lifetime touchdowns. Measurement results using a prototype indicate that the proposed architecture can be used to conduct manufacturing tests up to 38.6 GHz with less than -1-dB insertion loss while maintaining 11.4-m\(\Omega \) contact resistance. The measured return loss of the probe at 39.6 GHz is -12.05 dB.

A MEMS based device interface board

At gigahertz frequency range, performance degradation of the device interface board increases the yield loss and the cost of manufacturing. In this poster a MEMS based solution is proposed to design a Device Interface Board (DIB) supporting high-speed connectivity between the device under test and the tester. Simulation results indicate that the proposed scheme can operate up to 50 GHz without considerable signal integrity degradation.

A signal integrity enhancement technique for high speed test systems

Signal integrity degradation at high frequencies affects test results and increases the yield loss of integrated circuits. Parasitic effects and electromagnetic coupling due to transmission lines degrade the integrity of test signals and undermine the accuracy of the measurement results. A new signal integrity enhancement technique is presented in this paper to compensate the signal loss. A Proportional-Integrator-Differentiator (PID) circuit is implemented as an overshoot generator to negate the undesired effects of transmission lines. Simulation results at 1GHz show that the proposed method can improve the rise and fall time by orders of magnitude, and increase the eye-opening by more than 40%.

Built-In Self-Test for Capacitive MEMS Using a Charge Control Technique

A new Built-in Self-Test (BIST) method for capacitive Micro-Electrical-Mechanical System (MEMS) devices using charge-control method has been developed in which the Device Under Test (DUT) is stimulated through current sources. The DUT output signals are first converted to time domain intervals and then measured through a precision Time-to-Digital converter (TDC). The proposed BIST scheme supports self-calibration and produces robust results under process, supply and temperature variations. Simulation results indicate that this method can successfully detect minor structural defects altering the MEMS nominal capacitance by 70af.

Charge-Controlled Readout and BIST Circuit for MEMS Sensors

In this paper, we present a new readout circuit with an integrated built-in self-test (BIST) structure for capacitive microelectromechanical system (MEMS). In the proposed solution, instead of commonly used voltage control signals to test the device, charge-controlled stimuli are employed to cover a wider range of structural defects. The proposed test solution eliminates the risk of structural collapse in the test phase for gap-varying parallel-plate MEMS devices. Measurement results using a prototype fabricated in TSMC 65-nm CMOS technology indicate that the proposed BIST scheme can successfully detect minor structural defects altering MEMS nominal capacitance.