Nabil A. Ismail

Texture Recognition Based Natural Gray Images Coloring Technique

In this paper, we propose a new technique for computer coloring gray scale images. This technique works for texture based images like natural scenes. Its based on segmenting the image into different regions according to their textures and then classifying these textures to predefined texture classes to get their real colors. Recognition of these textures is performed by matching these textures with a training set stored in a special database. Most of authors working in coloring of gray scale images have used primitive methods for coloring which are both inaccurate and limited. At the end of this paper we show that our coloring system has succeeded to colorize the natural gray images with real colors in high quality.

Hardware Implementation of Efficient Modified Karatsuba Multiplier Used in Elliptic Curves

The efficiency of the core Galois field arithmetic improves the performance of elliptic curve based public key cryptosystem implementation. This paper describes the design and implementation of a reconfigurable Galois field multiplier, which is implemented using field programmable gate arrays (FPGAs). The multiplier of Galois field based on Karatsubas divide and conquer algorithm allows for reasonable speedup of the top-level public key algorithms. Binary Karatsuba multiplier is more efficient if it is truncated at n-bit multiplicand level and use an efficient classic multiplier algorithm. In these work three levels to truncate Binary Karatsuba algorithm (4 bits, 8 bits and 16 bits) are chosen showing that 8 bits is the best level for minimum number of slices and time delay to truncate Binary Karatsuba algorithm which is designed on an Xilinx VirtexE XCV2600 FPGA device. The VHDL hardware models are building using Xilinx ISE foundation software. This work is able to compute GF (2191) multiplication in 45.889 ns. experimental results of comparing block and stream ciphers when used to secure VoIP in terms of end-to-end delay and subjective quality of perceived voice.

Automated testing of java menu-based GUIs using XML visual editor

A common method for GUI testing is the capture and replay (CR) technique. While the commonly used of CR technique can not be used until an application under test (AUT) is completely developed. In this paper we propose a specification-driven approach to test menu-based Java GUI programs as an alternative to the CR technique. We introduce a GUI-event test specification language based on XML from which an automated test engine is generated. The popularity of XML as a scripting language is ease of use and its standard format. Along with our visual test scripts editor have made writing a test script using our proposed method is easy task. Beside the ability to test AUT before being completely developed, we have implemented another visual module that can generate the test specification file for an already existing AUT by using only the executable file of the program (.class). The engine generates GUI events and captures its responses automatically to verify the results of the test cases, which are written to a test log file. This engine supports the menu-based GUIs that became very popular these days in programs interfaces.

An Efficient Objects Compression Method by Minimizing Objects Number of an Image

In this paper a new lossless objects compression method for images is proposed. The proposed method first the pixels number of all objects within an image and, then, it minimizes the number of these objects without loss for the image content. This method includes three techniques to choose the objects that will be compressed. In the first technique, all objects within the image are compressed without the largest object. In the second technique, the objects of image are grouped (group by group) depend on their color, and the entire groups are compressed except the largest group. In the third technique, the image objects are compressed, except both the largest group and the objects that have similar objects in shape. To achieve a good value of compression ratio the proposed techniques are combined with other compression methods such as Huffman and differential encoding.

A texture recognition coloring technique for natural gray images

Gray image coloring is utilized to increase the visual appeal of images such as old black and white photos, movies or scientific illustrations. Most of authors working in coloring of gray scale images have used primitive methods for coloring which are both inaccurate and limited. In this paper we propose a new technique for computer coloring gray scale images. This technique works for texture based images like natural scenes. Its based on segmenting the image into different regions according to their textures. Real colors of the image can then be obtained by classifying these textures to predefined texture classes. Recognition of these textures is performed by matching these textures with a training set stored in a special database. We validate the efficiency of our coloring system by coloring several sets of natural gray images with high quality real colors.

Reconfigurable Implementation of Karatsuba Multiplier for Galois Field in Elliptic Curves

The efficiency of the core Galois field arithmetic improves the performance of elliptic curve based public key cryptosystem implementation. This paper describes the design and implementation of a reconfigurable Galois field multiplier, which is implemented using field programmable gate arrays (FPGAs). The multiplier of Galois field based on karatsuba’s divide and conquer algorithm allows for reasonable speedup of the top-level public key algorithms. Binary Karatsuba multiplier is more efficient if it is truncated at n-bit multiplicand level and use an efficient classic multiplier algorithm. In these work three levels to truncate Binary karatsuba algorithm (4 bits, 8 bits and 16 bits) are chosen showing that 8 bits is the best level for minimum number of slices and time delay to truncate Binary karatsuba algorithm which is designed on a Xilinx VirtexE XCV2600 FPGA device. The VHDL hardware models are building using Xilinx ISE foundation software. This work is able to compute GF(2191) multiplication in 45.889 ns.

FPGA Implementation of Elliptic Curve Point Multiplication over GF(2191)

Hardware acceleration of cryptographic algorithms is beneficial because considerable performance improvements can be attained compared to software implementations. Thus, hardware implementations can be used in critical applications requiring high encryption or decryption speeds. Parallel architecture with efficient hardware implementation of Galois field arithmetic operations is used to produce high speed computation time for the scalar multiplication operation which is the main operation in Elliptic Curve Cryptography (ECC) system. This work proposed a modification in karatsuba-ofman algorithm which is one of the best algorithms used to perform multiplication operation over Galois field. The modification contrasted on truncating karatsuba-ofman algorithm in a low level and using the classic polynomial multiplication algorithm. In addition, this work proposed architecture for implementing ECC on hardware using Montgomery algorithm in projective coordinates. The results show that the proposed architecture is able to compute GF(2^191) elliptic curve scalar multiplication operations in 72.939 μs on Xilinx Virtex-II XC2V6000 FPGA device and 100.68 μs on Xilinx VirtexE 2600. Also, the proposed architecture can be changed to be suitable for any arbitrary Galois field size with little modifications.

Specification-driven automated testing of java swing GUIs using XML

A common method for GUI testing is the capture and replay (CR) technique. While commonly used this technique can not be used until an application under test (AUT) is completely developed. In this paper we propose a specification-driven approach to test GUI-Based Java programs as an alternative to the CR technique. We introduce a GUI-event test specification language based on XML from which an automated test engine is generated. The popularity of XML as a scripting language, its ease of use and its standard format have made writing a test script using our proposed specification language an easy task. Beside the ability to test AUT before being completely developed we have implemented a visual editor that can generate the test specification file for an already existing AUT. The engine generates GUI events and captures event responses to automatically verify the results of the test cases which are written to a test log file. This approach supports N-version testing, where each version of the application is intended to satisfy the same specification.

Privacy preserving association rules mining on distributed homogenous databases

Privacy is one of the most important properties that an information system must satisfy. In these systems, there is a need to share information among different, not trusted entities, and the protection of sensible information has a relevant role. A relatively new trend shows that classical access control techniques are not sufficient to guarantee privacy preserving when data mining techniques are used in a malicious way. Privacy preserving data mining algorithms have been recently introduced with the aim of preventing the discovery of sensible information. In this paper, we propose a modification to privacy preserving association rule mining algorithm on distributed homogenous database. Our algorithm is faster, privacy preserving and provides accurate results. The flexibility for extension to any number of sites can be achieved without any change in the implementation. Also any increase in number of these sites does not add more time overhead, because all client sites perform the mining process in the same time so the overhead is in communication time only. Finally, the total bit-communication cost for our algorithm is function in (N) sites.

Evaluation of dynamic branch predictors for modern ILP processors

Abstract Modern instruction-level parallel (ILP) processors use superscalar architectures with deep pipelines in order to execute multiple instructions per cycle. The frequency and behavior of branch instructions seriously hinder performance of ILP processors. Various mechanisms, both at the compiler, as well as the processor level, have been proposed to predict the branch behavior. This work investigates various dynamic branch predictors at processor level to do a fair comparison among them. An experimental framework has been described using eight SPECint95 benchmarks and similar key parameters for evaluating these predictors. The performance impact of branch misprediction, the instruction-window size, machine width, the predictor size, first-level instruction-cache size, and history register length has been investigated. The hardware cost effectiveness of the different schemes is discussed.