Nadia Vandenbroeck

Directed self-assembly process integration: fin patterning approaches and challenges

Resolution requirements for photolithography have reached beyond the wavelength of light. Consequently, it is becoming increasingly complicated and expensive to further minimize feature dimensions as required to push the limits of Moore’s law. EUV lithography has been the much anticipated solution; however, its insertion timing for High Volume Manufacturing is still an uncertainty due to source power and EUV mask infrastructure limitations. Extending the limits of 193nm immersion lithography requires pitch division using either Double Patterning Pitch Division (DPPD), and/or Spacer Based Pitch Division (SBPD) schemes (e.g. Hard mask image transfer methods (Double, Triple, Quadruple)). While these approaches reduce pitch, there is an associated risk/compromise of process complexity, and overlay accuracy budget issues. Directed Self Assembly (DSA) processes offer the promise of providing alternative ways to extend optical lithography cost-effectively for sub-10nm nodes and present itself as an alternative pitch division approach. As a result, DSA has gained increased momentum in recent years, as a means for extending optical lithography past its current limits. The availability of a DSA processing line can enable to further push the limits of 193nm immersion lithography and overcome some of the critical concerns for EUV lithography. Robust etch transfer of DSA patterns into commonly used device integration materials such as silicon, silicon nitride, and silicon dioxide had been previously demonstrated [1,2]. However DSA integration to CMOS process flows, including cut/keep structures to form fin arrays, is yet to be demonstrated on relevant film stacks (front-end-of-line device integration such as hard mask stacks, and STI stacks). Such a demonstration will confirm and reinforce its viability as a candidate for sub-10nm technology nodes.

Defect mitigation and root cause studies in IMEC's 14nm half-pitch chemo-epitaxy DSA flow

High defect density in thermodynamics driven DSA flows has been a major cause of concern for a while and several questions have been raised about the relevance of DSA in high volume manufacturing. The major questions raised in this regard are: 1. What is the intrinsic level of DSA-induced defects, 2. Can we isolate the DSA-induced defects from the other processes-induced defects, 3. How much do the DSA materials contribute to the final defectivity and can this be controlled, 4. How can we understand the root causes of the DSA-induced defects, their kinetics of annihilation and finally, 5. Can we have block co-polymer anneal durations that are compatible with standard CMOS fabrication techniques (in the range of minutes) with low defect levels. This manuscript addresses these important questions and identifies the issues and the level of control needed to achieve a stable DSA defect performance.

Progress in directed self-assembly hole shrink applications

Directed Self-Assembly (DSA) has become a promising alternative for generating fine lithographic patterns. Since contact holes are among the most difficult structures to resolve through traditional lithographic means, directed selfassembly applications that generate smaller contact holes are of particular interest to the industry. In this paper, DSA integrations that shrink pre-patterned contact holes were explored. The use of both block copolymers (BCPs)1 and blended polymer systems2 was considered. In addition, both wet3 and dry4 techniques were used to develop the central core out of the respective phase-separated morphologies. Finally, the hole patterns created through the various contact hole applications were transferred to substrates of interest with the goal of incorporating them into an IMEC 28 nm node via chain electrical test vehicle for direct, side-by-side comparison.

Top coat or no top coat for immersion lithography

Since the moment immersion lithography appeared in the roadmaps of IC manufacturers, the question whether to use top coats has become one of the important topics for discussions. The top coats used in immersion lithography have proved to serve as good protectors from leaching of the resist components (PAGs, bases) into the water. However their application complicates the process and may lead to two side effects. First, top coats can affect the process window and resist profile depending on the materials refractive index, thickness, acidity, chemical interaction with the resist and the soaking time. Second, the top coat application may increase the total amount of defects on the wafer. Having an immersion resist which could work without the top coat would be a preferable solution. Still, it is quite challenging to make such a resist as direct water/resist interaction may also result in process window changes, CD variations, generation of additional defects. We have performed a systematic evaluation of a large number of immersion resist and top coat combinations, using the ASML XT:1250Di scanner at IMEC. The samples for the experiments were provided by all the leading resist and top coat suppliers. Particular attention was paid to how the resist and top coat materials from different vendors interacted with each other. Among the factors which could influence the total amount of defects or CD variations on the wafer were: the materials dynamic contact angle and its interaction with the scanner stage speed, top coat thickness and intermixing layer formation, water uptake and leaching. We have examined the importance of all mentioned factors, using such analytical techniques as Resist Development Analyser (RDA), Quartz Crystal Microbalance (QCM), Mass Spectroscopy (MS) and scatterometry. We have also evaluated the influence of the pre- and pos- exposure rinse processes on the defectivity. In this paper we will present the data on imaging and defectivity performance of the resists with and without the use of top coats. So far we can conclude that top coat/resist approach used in immersion lithography needs some more improvements (i.e. process, materials properties) in order to be implemented in high volume manufacturing.

Toward sub-20nm pitch Fin patterning and integration with DSA

Directed Self Assembly (DSA) has gained increased momentum in recent years as a cost-effective means for extending lithography to sub-30nm pitch, primarily presenting itself as an alternative to mainstream 193i pitch division approaches such as SADP and SAQP. Towards these goals, IMEC has excelled at understanding and implementing directed self-assembly based on PS-b-PMMA block co-polymers (BCPs) using LiNe flow [1]. These efforts increase the understanding of how block copolymers might be implemented as part of HVM compatible DSA integration schemes. In recent contributions, we have proposed and successfully demonstrated two state-of-the-art CMOS process flows which employed DSA based on the PS-b-PMMA, LiNe flow at IMEC (pitch = 28 nm) to form FinFET arrays via both a ‘cut-last’ and ‘cut-first’ approach [2-4]. Therein, we described the relevant film stacks (hard mask and STI stacks) to achieve robust patterning and pattern transfer into IMEC’s FEOL device film stacks. We also described some of the pattern placement and overlay challenges associated with these two strategies. In this contribution, we will present materials and processes for FinFET patterning and integration towards sub-20 nm pitch technology nodes. This presents a noteworthy challenge for DSA using BCPs as the ultimate resolution for PS-b-PMMA may not achieve such dimensions. The emphasis will continue to be towards patterning approaches, wafer alignment strategies, the effects of DSA processing on wafer alignment and overlay.

Process optimization of templated DSA flows

Directed Self-Assembly (DSA) of Block Co-Polymers (BCP) has become an intense field of study as a potential patterning solution for future generation devices. The most critical challenges that need to be understood and controlled include pattern placement accuracy, achieving low defectivity in DSA patterns and how to make chip designs DSA-friendly. The DSA program at imec includes efforts on these three major topics. Specifically, in this paper the progress in setting up flows for templated DSA within the imec program will be discussed. A process has been implemented based on a hard mask as the template layer. In this paper primarily the impact of local pattern density and BCP film thickness on the templated DSA process are discussed. The open hole rate and the placement accuracy of BCP patterns within the template are the primary figures of merit.

15nm HP patterning with EUV and SADP: key contributors for improvement of LWR, LER, and CDU

This paper discusses the approach for patterning 15nm Half Pitch (HP) structures using EUV lithography combined with Self-Aligned Double Patterning (SADP). A stack composed of a double hard mask, which allows decoupling photoresist transfer and trim, and an α-Si mandrel, which offers better mechanical properties during the mandrel and spacer patterning, is proposed. A break-down study with the patterning steps was performed to investigate the key contributors for improvement of LWR, LER and CDU, targeting integrated solutions with lithography, etch, thin film deposition, and wet cleans for selected applications. Based on the optimization of these key patterning contributors, optimum LWR, LER and CDU at 15nm HP are demonstrated.

Litho-process-litho for 2D 32nm hp Logic and DRAM double patterning

Over the last couple of years a lot of attention has gone to the development of new Litho-Process-Litho-Etch (LPLE) double patterning process alternatives to Litho-Etch-Litho-Etch (LELE) or Spacer-Defined Double Patterning (SDDP)[3,5,6]. Much progress has been made on the material side to improve the resolution of these processes and imaging down to 26nm and even 22 nm 1:1 Lines/Spaces has been demonstrated[1,2,13]. This shows that from a resolution point of view these processes can bridge the gap between ArF immersion single patterning and EUV lithography. These results at small pitches are typically obtained using dipole illumination making them only useful for one pitch-one orientation. Applying the combination of double patterning and dipole illumination is thus limited to regular line/space gratings. For this paper, the patterning of more random 2D and through pitch designs is investigated using the double patterning LPL alternatives for the POLY layer in combination with annular illumination. Fundamental behaviors of the freezing schemes that affect the patterning performance for logic applications are discussed.

Measurement and evaluation of water uptake by resists, top coats, stacks, and correlation with watermark defects

With immersion lithography approaching the insertion in production, watermarks remain as one of the main concerns for immersion specific defects. They require special attention because of their size and associated high kill-ratio, and their increasing occurrence at higher scan speeds. IMEC has been working to understand the underlying mechanism of why remaining water droplets cause these defects. This work focuses on water uptake measurements and how this parameter correlates to watermark defectivity. Ellipsometric Porosimetry (EP) is used to measure the water uptake tendencies of resist and top coat materials and stacks thereof, and investigate what parameters are affecting it. The influence of material and process parameters and the presence of a top coat on water uptake by the resist are evaluated. In parallel, the quartz crystal microbalance (QCM) technique has been used as an alternative option to measure the water uptake. Though a one-to-one comparison between the results is not straightforward, the main trends are identical for both techniques. No perfect correlation of watermark defectivity with water uptake has been found in this study. Nevertheless, the results show a tendency towards higher watermark sensitivity with higher water uptake by the film. It is recognized that the total watermark defectivity is most probably a complex interplay of different parameters with water uptake being only one of them.

DSA materials contributions to the defectivity performance of 14nm half-pitch LiNe flow at IMEC

This manuscript shows the relationship between defectivity of a typical chemo-epitaxy sequence and the DSA-specific materials, namely the mat, the brush and the block co-polymer. We demonstrate that the density of assembly defects in a line-space DSA flow, namely the dislocations and 1-period bridges have a direct correlation to certain parameters in the synthesis sequence of these materials. The primary focus of this manuscript is on identifying, controlling and reproducing the defects-critical parameters in the block co-polymer synthesis process for a stable and low defect performance of DSA flows.