Nadine Collaert

Analysis of the parasitic S/D resistance in multiple-gate FETs

The multiple-gate field-effect transistor (FET) is a promising device architecture for the 45-nm CMOS technology node. These nonplanar devices suffer from a high parasitic resistance due to the narrow width of their source/drain (S/D) regions. We analyze the parasitic S/D resistance behavior of the multiple-gate FETs using a novel, S/D geometry-based analytical model, which is validated using three-dimensional device simulations and experimental results. The model predicts limits to parasitic S/D resistance scaling, which reveal that the contact resistance between the S/D silicide and Si-fin dominates the parasitic S/D resistance behavior of multiple-gate FETs. It is shown that the selective epitaxial growth of Si on S/D regions alone may be insufficient to meet the semiconductor roadmap target for parasitic S/D resistance at the 45-nm CMOS technology node.

Transport Spectroscopy of a Single Dopant in a Gated Silicon Nanowire

We report on spectroscopy of a single dopant atom in silicon by resonant tunneling between source and drain of a gated nanowire etched from silicon on insulator. The electronic states of this dopant isolated in the channel appear as resonances in the low temperature conductance at energies below the conduction band edge. We observe the two possible charge states successively occupied by spin-up and spin-down electrons under magnetic field. The first resonance is consistent with the binding energy of the neutral D0 state of an arsenic donor. The second resonance shows a reduced charging energy due to the electrostatic coupling of the charged D- state with electrodes. Excited states and Zeeman splitting under magnetic field present large energies potentially useful to build atomic scale devices.

Disorder-controlled-kinetics model for negative bias temperature instability and its experimental verification

A model for NBTI is proposed based on disorder-controlled diffusion and drift in amorphous dielectrics. Experimental data on finFETs confirm all major predictions of the model: temperature dependence of the NBTI exponent, non-Arrhenius behavior of NBTI, log(t) and electric field dependencies of recovery. Experimental challenges with determining NBTI parameters are also highlighted.

Planar Bulk MOSFET s Versus FinFETs: An Analog/RF Perspective

Comparison of digital and analog figures-of-merit of FinFETs and planar bulk MOSFETs reveals an interesting tradeoff in the analog/RF design space. It is found that FinFETs possess the following key advantages over bulk MOSFETs: reduced leakage, excellent subthreshold slope, and better voltage gain without degradation of noise or linearity. This makes them attractive for digital and low-frequency RF applications around 5 GHz, where the performance-power tradeoff is important. On the other hand, in high-frequency applications, planar bulk MOSFETs are seen to hold the advantage over FinFETs due to their higher peak transconductance. However, this comes at a cost of a reduced voltage gain of bulk MOSFETs

Direct Measurement of Top and Sidewall Interface Trap Density in SOI FinFETs

Conventional charge pumping is demonstrated on triple-gate silicon-on-insulator FinFET gated-diode structures with varying fin widths. A simple technique is proposed and verified allowing to independently estimate fin top and sidewall interface trap density. A higher interface state density on the sidewalls is observed, which is attributed to higher fin sidewall roughness. The methodology is also demonstrated to be sensitive to fin sidewall surface crystallographic orientation. The technique presents a straightforward means of assessing the fin sidewall and topwall interface quality, which can then be directly correlated with both processing influences and reliability effects

Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography

We investigate scalability, performance and variability of high aspect ratio trigate FinFETs fabricated with 193 nm immersion lithography and conventional dry etch. FinFETs with fin widths down to 5nm are achieved with record aspect ratios of 13. Excellent nMOS and pMOS performance is demonstrated for narrow fins and short gates. Further improvement in nMOS performance can be achieved by eliminating access resistance that is currently attributed to poor re-crystallization of implantation damage in narrow fins. Fully-depleted FinFETs show strongly improved short channel effect (SCE) control when the fin width is scaled, even without halo-implants. Nearly ideal DIBL and sub-threshold slope (SS) are achieved down to 30nm gate length. Low leakage devices are realized by combining a fully depleted channel, HfSiO high-k dielectric, mid-gap TiN metal electrodes, and aggressive fin width scaling. Symmetrical threshold voltages (±0.35 V) are achieved. It is demonstrated that selective epitaxial growth on source and drain regions is essential to limit parasitic resistance in narrow fin devices. Parametric spread is dominated by gate length variations in short devices but within-die fin width variations are still evident for long devices.

Multi-gate devices for the 32nm technology node and beyond

Due to the limited control of the short channel effects, the high junction leakage caused by band-to-band tunneling and the dramatically increased VT statistical fluctuations, the scaling of planar bulk MOSFETs becomes more and more problematic with every technology node. The ITRS roadmap predicts that from the 32 nm technology node on planar bulk devices will not be able to meet the stringent leakage requirements anymore and that multi-gate devices will be required. In this paper, the suitability of FinFET based multi-gate devices for the 32 nm technology and beyond will be discussed. Apart from the benefits, some technological challenges will be addressed.

Review of FINFET technology

Although at single transistor and small circuits level, FINFET technology has been demonstrated to be an attractive option for advanced technology nodes, there are still important challenges to face like reduction of access resistance and the implementation of strain boosters in both NMOS and PMOS FINFET devices. The high performance sensitivity to fin dimensions (width, height, LER) sets up very tight restrictions for the process control which may create a big challenge to demonstrate process manufacturability.

Optimizing the Readout Bias for the Capacitorless 1T Bulk FinFET RAM Cell

In this letter, we demonstrate a one-transistor capacitorless DRAM on standard bulk FinFET, using no additional processing. It is shown that, due to the use of the ground-plane doping and optimization of the READ bias conditions, no special process adjustment is required to obtain wide programming windows and long retention times, even for fin widths down to 20 nm.

Heteroepitaxy of InP on Si(001) by selective-area metal organic vapor-phase epitaxy in sub-50 nm width trenches: The role of the nucleation layer and the recess engineering

This study relates to the heteroepitaxy of InP on patterned Si substrates using the defect trapping technique. We carefully investigated the growth mechanism in shallow trench isolation trenches to optimize the nucleation layer. By comparing different recess engineering options: rounded-Ge versus V-grooved, we could show a strong enhancement of the crystalline quality and growth uniformity of the InP semiconductor. The demonstration of III-V heteroepitaxy at scaled dimensions opens the possibility for new applications integrated on Silicon.