Naehyuck Chang

On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches

Traditionally, design-space exploration for systems-on-chip (SoCs) has focused on the computational aspects of the problem at hand. However, as the number of components on a single chip and their performance continue to increase, a shift from computation-based to communication-based design becomes mandatory. As a result, the communication architecture plays a major role in the area, performance, and energy consumption of the overall system. This article presents a comprehensive evaluation of three on-chip communication architectures targeting multimedia applications. Specifically, we compare and contrast the network-on-chip (NoC) with point-to-point (P2P) and bus-based communication architectures in terms of area, performance, and energy consumption. As the main contribution, we present complete P2P, bus-, and NoC-based implementations of a real multimedia application (i. e. the MPEG-2 encoder), and provide direct measurements using an FPGA prototype and actual video clips, rather than simulation and synthetic workloads. We also support the experimental findings through a theoretical analysis. Both experimental and analysis results show that the NoC architecture scales very well in terms of area, performance, energy, and design effort, while the P2P and bus-based architectures scale poorly on all accounts except for performance and area, respectively.

DLS: dynamic backlight luminance scaling of liquid crystal display

Backlight systems dominate the power requirements of battery-operated hand-held devices with color thin-film transistor (TFT), liquid crystal displays (LCDs). We introduce dynamic luminance scaling of the backlight with appropriate image compensation. Dynamic backlight luminance scaling (DLS) keeps the perceived intensity or contrast of the image as close as possible to the original while achieving significant power reduction. DLS compromises quality of image between power consumption, which fulfills a large variety of user preferences in power-aware multimedia applications. DLS saves 20% to 80% of power consumption of the backlight systems while keeping a reasonable amount of image quality degradation.

Low-power color TFT LCD display for hand-held embedded systems

An LCD (Liquid Crystal Display) is a standard display device for hand-held embedded systems. Today, color TFT (Thin-Film Transistor) LCDs are common even in cost-effective equipments. An LCD display system is composed of an LCD panel, a frame buffer memory, an LCD and frame buffer controller, and a backlight inverter and lamp. All of them are heavy power consumers, and their portion becomes much more dominant when running interactive applications. This is because interactive applications are often triggered by human inputs and thus result in a lot of slack time in the CPU and memory system, which can be effectively used for dynamic power management.

DC–DC Converter-Aware Power Management for Low-Power Embedded Systems

Most digital systems are equipped with dc-dc converters to supply various levels of voltages from batteries to logic devices. DC-DC converters maintain legal voltage ranges regardless of the load current variation as well as battery voltage drop. Although the efficiency of dc-dc converters is changed by the output voltage level and the load current, most existing power management techniques simply ignore the efficiency variation of dc-dc converters. However, without a careful consideration of the efficiency variation of dc-dc converters, finding a true optimal power management will be impossible. In this paper, we solve the problem of energy minimization with the consideration of the characteristics of power consumption of dc-dc converters. Specifically, the contributions of our work are as follows: 1) We analyze the effects of the efficiency variation of dc-dc converters on a single-task execution in dynamic voltage scaling (DVS) scheme and propose the technique for dc-dc converter-aware energy-minimal DVS. 2) is then extended to embed an awareness of the characteristics of dc-dc converters in general DVS techniques for multiple tasks. 3) We go on to propose a technique called for generating a dc-dc converter that is most energy efficient for a particular application. 4) We also present an integrated framework, i.e., , based on and , which addresses dc-dc converter configuration and DVS simultaneously. Experimental results show that is able to save up to 24.8% of energy compared with previous power management schemes, which do not consider the efficiency variation of dc-dc converters.

Hybrid electrical energy storage systems

Electrical energy is a high quality form of energy that can be easily converted to other forms of energy with high efficiency and, even more importantly, it can be used to control lower grades of energy quality with ease. However, building a cost-effective electrical energy storage (EES) system is a challenging task despite steady advances in the design and manufacturing of EES elements including various battery and supercapacitor technologies. As of today, no single type of EES element fulfills high energy density, high power delivery capacity, low cost per unit of storage, long cycle life, low leakage, and so on at the same time. Unlike conventional EES systems, we introduce a HEES (hybrid EES) system comprising heterogeneous EES elements. Our proposed HEES system builds on the concepts of computer memory system architecture and management in order to achieve the attributes of an ideal EES system through appropriate allocation and organization of various types of EES elements. We also introduce a HEES design considerations which should be taken into account to optimize the amortized cost for the system, including the initial cost (cost per capacity), the operating cost (efficiency), the maintenance cost (cycle life and disposal cost), and so forth.

Energy- and endurance-aware design of phase change memory caches

Phase change memory (PCM) is one of the most promising technology among emerging non-volatile random access memory technologies. Implementing a cache memory using PCM provides many benefits such as high density, non-volatility, low leakage power, and high immunity to soft error. However, its disadvantages such as high write latency, high write energy, and limited write endurance prevent it from being used as a drop-in replacement of an SRAM cache. In this paper, we study a set of techniques to design an energy- and endurance-aware PCM cache. We also modeled the timing, energy, endurance, and area of PCM caches and integrated them into a PCM cache simulator to evaluate the techniques. Experiments show that our PCM cache design can achieve 8% of energy saving and 3.8 years of lifetime compared with a baseline PCM cache having less than a hour of lifetime.

Accurate modeling and calculation of delay and energy overheads of dynamic voltage scaling in modern high-performance microprocessors

Dynamic voltage and frequency scaling (DVS) has been studied for well over a decade, and even commercial systems widely support DVS nowadays. Nevertheless, existing DVS transition overhead models do not accurately reflect modern DVS architectures including modern DC-DC converters, PLL (Phase Lock Loop), and voltage and frequency change policies. Incorrect DVS overhead models prevent one from achieving the maximum energy gain, by misleading the DVS control policies. This paper introduces an accurate DVS overhead model, in terms of both energy consumption and time penalty, through detailed observation of modern DVS setups and voltage and frequency change guidelines from vendors. We introduce new major contributors to the DVS overhead including the performance underdrive loss of the DVS-enabled microprocessor, additional inductor IR loss, and so on, as well as consideration of power efficiency from discontinuous-mode DC-DC conversion. Our DVS overhead model enhances the DVS overhead model accuracy from 86% to 238% for Intel Core2 Duo E6850 and LTC3733.

A backlight power management framework for battery-operated multimedia systems

Thin-film transistor liquid-crystal displays are systems widely used to support full-featured multimedia. For such systems, backlight is a major source of power dissipation. This article introduces a backlight power management framework and explores trade-offs in the extended dynamic-luminance-scaling design space in terms of energy reduction, performance penalty, and image quality.

Cycle-accurate energy consumption measurement and analysis: case study of ARM7TDMI

We introduce an energy consumption analysis of complex digital systems through a case study of ARM7TDMI RISC processor by using a new energy measurement technique. We developed a cycle-accurate energy consumption measurement system based on charge transfer which is robust to spiky noise and is capable of collecting a range of power consumption profiles in real time. The relative energy variation of the RISC core is measured by changing the opcode, the instruction fetch address, the register number, in each pipeline stage, respectively. We demonstrated energy characterization of a pipelined RISC processor for high-level power reduction.

Dynamic voltage scaling of OLED displays

Unlike liquid crystal display (LCD) panels that require high-intensity backlight, organic LED (OLED) display panels naturally consume low power and provide high image quality thanks to their self-illuminating characteristic. In spite of this fact, the OLED display panel is still the dominant power consumer in battery-operated devices. As a result, there have been many attempts to reduce the OLED power consumption. Since power consumption of any pixel of the OLED display depends on the color that it displays, previous power saving methods change the pixel color subject to a tolerance level on the color distortion specified by the users. In practice, the OLED power saving techniques cannot be used on common user applications such as photo viewers and movie players. This paper introduces the first OLED power saving technique that does not result in a significant degradation in the color and luminance values of the displayed image. The proposed technique is based on dynamic (driving) voltage scaling (DVS) of the OLED panel. Although the proposed DVS technique may degrade luminance of the panel, the panel luminance can be restored with appropriate image compensation. Consequently, power is saved on the OLED display panel with only minor changes in the color and luminance of the image. This technique is similar to dynamic backlight scaling of LCDs, but is based on the unique characteristics of the OLED drivers. The proposed method saves wasted power in the driver transistor and the internal resistance with an amplitude modulation driver, and in the internal resistance with a pulse width modulation driver, respectively. Experimental results show that the proposed OLED DVS with image compensation technique saves up to 52.5% of the OLED power while keeping the same human-perceived image quality for the Lena image.