Nagaraj C. Shivaramaiah

Time-Multiplexed Offset-Carrier QPSK for GNSS

A new method of time-multiplexing quadrature phase shift keying (QPSK) signals modulated by a complex subcarrier is proposed. In its simplest form the proposed time-multiplexed off-set carrier quadrature phase shift keying (TMOC-QPSK) can replace the constant-envelope alternate binary offset carrier (AltBOC) currently used for some Global Navigation Satellite System (GNSS) signals. The signal structure is described focusing on the signal generation methodology, power spectral density (PSD), and correlation function in comparison with the alternate binary offset carrier (AltBOC) modulation first used for the Galileo E5 signal. It is shown that the PSD and correlation functions match exactly to those of an AltBOC modulated signal. A method to realize the correlator for the proposed TMOC-QPSK signal is described, and the complexities compared with AltBOC are presented. A field-programmable gate array (FPGA)-based implementation shows that the core TMOC-QPSK correlator requires 32% less hardware resources and consumes 23% less power compared with an AltBOC correlator.

Significance of Cell-Correlation Phenomenon in GNSS Matched Filter Acquisition Engines

Modern Global Navigation Satellite Systems (GNSS) are going to provide new signals with longer PRN codes and higher chipping rates, which aim to improve the positioning performance with respect to the current GPS. However, these new characteristics also cost GNSS receivers a high computational complexity. Due to their attractive acquisition time performance, matched filter (MF) correlators promise to be a good choice for GNSS signal acquisition engines. Existing methods to evaluate GNSS signal acquisition engine performance parameters, viz. detection probabilities and mean acquisition time, assume that the detections among the neighboring test cells are independent. However in a matched filter correlator, depending on the spacing between the test cells, due to the correlation of the local code with the noise component in the received signal at different time instances within a chip period, there can exist strong correlations, which affect these performance parameters. Also, the presence of cell correlations influences the acquisition threshold setting, which is a critical design parameter. This paper provides a detailed analysis of the significance of the cell-correlation phenomenon in MF correlators for the two widely used signal families in GNSS, namely BPSK and BOC, in particular BPSK(1) and BOC(1,1). Justifying the theoretical analysis with Monte Carlo simulations, it is shown that the maximum error in estimating the mean acquisition time without considering the cell-correlation phenomenon is shown to be about 10% for the BPSK(1) and about 12% for the BOC(1,1) signal.

On the baseband hardware complexity of modernized GNSS receivers

This paper discusses the resource and power requirements of baseband signal processing circuitry to process new Global Navigation Satellite Systems (GNSS) signals. The large signal bandwidth, multiple longer spreading codes and the split-spectrum modulations demand wider registers and wider accumulators at higher operating frequencies compared to the baseband hardware of the existing Global Positioning System (GPS) L1 Coarse/Acquisition (C/A) signal. Some of the signals with the memory spreading codes have a completely new requirement of up to 0.5 M memory bits. Implementation of the core baseband signal processing blocks in FPGA hardware reveals up to three times the resource requirement and up to thirty seven times the power consumption for high-end signals compared to the core baseband module of the existing L1 C/A signal.

A Novel Extended Tracking Range DLL for AltBOC Signals

Code tracking linear range and the code phase tracking jitter have always been opposing ends of the design criteria of a code lock loop in direct-sequence spread-spectrum communication systems. New modulation techniques used in Global Navigation Satellite Systems (GNSS) offer better code tracking jitter and multipath performance by sharpening the correlation triangle. However the linear tracking range is reduced which directly results in poor dynamics and low signal strength performance of the tracking loop. The problem is most severe in the sophisticated Alternate Binary Offset Carrier (AltBOC) modulation. This paper proposes a method to extend a loops tracking range without affecting the jitter performance in the existing linear range of the code tracking loop.

Feasibility analysis of baseband architectures for multi-GNSS receivers

Receiver design challenges arising from new GNSS signals include required intermediate frequency, sampling rate, modulation type, spreading code, and secondary code. Several architectures are examined here aiming at a best model for multi-GNSS implementation, especially the underlying baseband and software realization platform. In this pursuit, it is found that the multi-core and multiple processor architectures are promising candidates. General purpose processors or digital signal processors demand excessive resources and power consumption. Alternative architectures are presented along with the general cost function, used to evaluate architecture efficiency. Taking into account (1) the superiority of a hardware time-interleaving technique, (2) RAM-based design versus register-based design, and (3) careful consideration of modern GNSS signal attributes, the proposed programmable custom pipeline correlator core provides flexibility and significantly reduces resources and power.

A programmable multi-GNSS baseband receiver

This paper assesses the drawbacks in reconfigurability and resource consumption of the conventional baseband signal processing circuitry for modern Global Navigation Satellite Systems (GNSSs) signals. The involvement of new GNSSs leads to the requirement of designing a programmable multi-GNSS baseband receiver that can be reconfigured across GNSS signals. Paralleling baseband circuits is the easiest approach, but resource consumption will significant. Hardware time multiplexing is more effective technique. It, however, requires an efficient memory hierachy and an efficient code generator design. These challenges are tackled in the proposed architecture which utilises as 3.2%, 6.6%, 12.5% and 50% resources as the conventional baseband circuitry consisting of 16 GPS L1 C/A channels, 8 BEIDOU B1I channels, 4 GALILEO E1 channels, and 1 GPS L5 channel, respectively. Results are also justified by mathematical analysis.

A pipeline dynamically configured GNSSs baseband circuit

This paper proposes a pipeline programmable interleaved baseband circuitry for modern Global Navigation Satellite Systems (GNSSs) signals. The involvement of new GNSSs leads to the requirement of designing a programmable multi-GNSS baseband receiver that can be reconfigured across GNSS signals. The baseband circuit parallelism is the easiest approach, but resource consumption will be significant. Hardware time multiplexing is more effective technique. However, it requires an efficient memory hierachy and an efficient design. These challenges are tackled in the proposed architecture which utilises as 3.2%, 6.6%, 12.5% and 50% resources as the conventional baseband circuitry consisting of 16 GPS L1 C/A channels, 8 BEIDOU B1I channels, 4 GALILEO E1 channels, and 1 GPS L5 channel, respectively. The power consumption is also reduced by 29% to 70% compared to the corresponding conventional digital correlator circuits; while it is still meeting the timing constrain of the baseband receiver.

Baseband Hardware Designs in Modernised GNSS Receivers

The Global Positioning System (GPS) receiver has come a long way from being a specialised tool to a more general purpose everyday use mainstream gadget. This transformation is not only due to the advancements in semiconductor technology and embedded systems but also due to a highly concentrated research effort in the past decade that targeted a high performance, low power and affordable GPS receiver design. Before the ideas for such an efficient GPS receiver design could attain the saturation stage, the GPS modernisation and the development of several satellite navigation systems under the broader “Global Navigation Satellite Systems” (GNSS) umbrella, have brought a new dimension to the problem of efficient GNSS receiver design. The baseband signal processing engine forms an integral part of any GNSS receiver and is a key contributor to the overall cost and power consumption.

A Dynamically Configurable Decimator for a GNSS Baseband Receiver

Modern global navigation satellite system (GNSS) front ends sample the received radio-frequency signal at an intermediate frequency (IF) and, then, downconvert it to baseband in the digital domain. A locally generated spreading code is subsequently correlated with the baseband signal at the sampling frequency. This can mean that the receiver correlates at an unnecessarily high frequency (sometimes more than four times the chipping rate). The power consumption is, thus, high. If the baseband signal is downsampled after appropriate filtering, the correlator can process at a fraction of the sampling frequency. The power dissipation is considerably reduced as a result. Furthermore, by resampling at an integer submultiple of the sampling frequency, not only is downsampling jitter eliminated, but also architectural configurability in the correlator is possible, allowing further reductions in power and resource consumption. In this paper, a dynamically configurable decimator for a matched filter correlator is presented. The mathematical model of the signal processing is analyzed for various downsample rates. The effective postcorrelator signal-to-noise-plus interference ratio is estimated in theory and measured by experiment, illustrating that the proposed decimator correlator outperforms the resample IF correlator.

GNSS receiver implementations to mitigate the effects of commensurate sampling frequencies on DLL code tracking

The sampling frequency of a digitized intermediate frequency signal has a strong effect on the measurement accuracy of Global Navigation Satellite System (GNSS) receivers. The delay-locked loop tracking error is significant when the sampling frequency is an integer multiple of the code chipping rate, the so-called commensurate sampling frequency, and the number of distinct instantaneous residual code phases is low. This results in distortions of the correlation shape and discriminator functions that lead to a significant accuracy degradation. These effects are most pronounced when the sampling frequency is low. Notwithstanding, it is generally good for receivers to keep the sampling frequency to a minimum owing to the processing load and power consumption. It creates a challenge for existing GNSS signal processing techniques. Random, sine and sawtooth jitters have been found to mitigate these distortions considerably. A software algorithm and two hardware receiver implementations of these solutions are proposed. A register-based architecture can be directly applied to the conventional receiver architecture, while the increase in resource and power consumption is insignificant. A RAM-based design cannot only considerably minimize utilized resources but also slightly reduce the power consumption compared to the conventional architecture.