Nagesh Vasanthavada

Design of an image edge detection filter using the Sobel operator

The architecture of the edge detector presented is highly pipeline to perform the computations of gradient magnitude and direction for the output image samples. The chip design is based on a 2- mu m, double-metal, CMOS technology and was implemented using a silicon compiler system in less than 2 man-months. It is designed to operate with a 10-MHz two-phase clock, and it performs approximately 200*10/sup 6/ additions/s to provide the required magnitude and direction outputs every clock cycle. The function of the chip has been demonstrated with a prototype system that is performing image edge detection in real time. >

Synchronization of fault-tolerant clocks in the presence of malicious failures

The problem of achieving global clock synchronization in fault-tolerant clocks by preventing so-called multiple cliques in the presence of malicious clock failures (i.e. clock failures that are perceived differently by different nonfaulty clocks) is addressed. A solution to the problem, referred to as the averaging rule, is developed, and its use is analytically justified using the notions of clock partitions and generalized clock partitions. Experimental characterization of the multiple cliques problem has been undertaken, and certain conditions that induce their occurrence in practical hardware implementation are identified. The effects of clock-receiver triggering variations and phase-detector operating range on the instantaneous frequencies of the clock modules are investigated. The efficacy of the averaging rule is established not only by analysis but also by means of simulations and experimentation with hardware clock implementations. >

Testing of differential cascade voltage switch (DCVS) circuits

The problem of testing differential cascode voltage switch (DCVS) circuits is analyzed. These circuits have several potential applications in fault-tolerant, highly available system design due to their inherent self-checking capability. It is shown how concurrent (online) testing of DCVS circuits, which is very effective under single transistor fault assumptions, can be performed. The impact of multiple faults of DCVS circuits is examined, and analytical results are derived. These results indicate that periodic offline tests on DCVS circuits are necessary in order to achieve high multiple-fault coverage. Single-fault test sets and/or pseudorandom vectors were successfully used in the offline tests to detect many of the multiple faults which reduce the efficiency of online tests. The results show the need for a comprehensive mixed-test strategy combining offline and online tests for DCVS circuits. >

The Test Engineer's Assistant: a support environment for hardware design for testability

A description is given of TEA (Test Engineers Assistant), a CAD (computer-aided design) environment developed to provide the knowledge base and tools needed by a system designer for incorporating testability features into a design. TEA helps the designer meet the requirements of fault coverage and ambiguity group size. Fault coverage is defined as the percentage of faults that can be detected out of the population of all faults of a unit under test with a particular test set. An ambiguity group is defined as the smallest hardware entity in a given level of the system design hierarchy (that is, board, subsystem, and system) to which a fault can be isolated. The fault model considered throughout is the single stuck-at fault model. An example application of TEA is included.<<ETX>>

Design of fault-tolerant clocks with realistic failure assumptions

The authors address the problem of designing fault-tolerant, phase-locked clocks in the presence of different types of clock failures and show that significant improvements in hardware complexity and reliability can be achieved when failed clock modules are partitioned into two classes: malicious and nonmalicious. They show that the condition N>2t+max(t1, 1) is necessary and sufficient to tolerate up to t failed clock modules out of which a maximum of t1 can behave maliciously. The practical value of this design concept is demonstrated by examples.<<ETX>>

A new built-in test scheme for DCVS circuits

A new built-in-test (BIT) scheme for differential cascode voltage switch (DCVS) circuits is presented. The scheme implements a mixed test strategy, combining both offline and online tests, and achieves very high transistor-level fault coverage as well as low error detection latency. The scheme has the additional merits of minimal impact on circuit performance and very reasonable hardware overhead.<<ETX>>

A built-in test module for fault isolation

A broad-level implementation of signature analysis that uses a built-in test module called a testing switch is presented. It is shown how board designers can incorporate the testing-switch modules to reduce the time it takes to isolate faulty chips. Both the test time and the power overhead are better with the testing-switch implementation than with schemes using built-in logic block observer circuits. The proposed technique is especially useful when boundary scan and self-test cannot be implemented in every chip of a board.<<ETX>>

CAD tools for supporting system design for testability

A methodology and the supporting CAD (computer-aided design) tools are discussed for designing a digital system so that it can meet predefined testability requirements. The set of tools is called the Test Engineers Assistant (TEA). The TEA system creates an environment in which the designer can perform performance assessment, functional design, and design for testability (DFT). TEA is developed to support automated DFT at the board and subsystem levels, to aid in an appropriate choice of BIT (built-in test) techniques at the board level that is supported at the subsystem and system levels, to indicate where to augment system function with predefined BIT modules to increase testability, and to assess the hardware costs of implementing DFT and BIT.<<ETX>>

A monolithic scan-line bit producer for real-time image rasterization

Abstract This paper presents the design and implementation on a single chip of a special purpose circuit used for real-time data rasterization based on the scan-line algorithm. The chip functions as a peripheral to the processor that runs the scan-line algorithm and, under processor control, produces the bit patterns to be stored in a bit-map memory. Utilization of the chip allows the processor to perform just a “write” operation, instead of a “read-modify-write” operation, for every scan-line of data. This results in substantial performance improvement in the application of the scan-line algorithm for data rasterization. The circuit has been implemented in 3μ CMOS technology, and its function was demonstrated with up to 15 MHz of throughput. The design allows the interconnection of many chips to facilitate applications with scan-lines of any size. The throughput, however, remains constant at 15 MHz, independent of the scan-line size.