Nagib Hakim

Statistical static timing analysis: how simple can we get?

With an increasing trend in the variation of the primary parameters affecting circuit performance, the need for statistical static timing analysis (SSTA) has been firmly established in the last few years. While it is generally accepted that a timing analysis tool should handle parameter variations, the benefits of advanced SSTA algorithms are still questioned by the designer community because of their significant impact on complexity of STA flows. In this paper, we present convincing evidence that a path-based SSTA approach implemented as a post-processing step captures the effect of parameter variations on circuit performance fairly accurately. On a microprocessor block implemented in 90nm technology, the error in estimating the standard deviation of the timing margin at the inputs of sequential elements is at most 0.066 FO4 delays, which translates in to only 0.31% of worst case path delay.

QED: Quick Error Detection tests for effective post-silicon validation

Long error detection latency, the time elapsed between the occurrence of an error caused by a bug and its manifestation as a system-level failure, is a major challenge in post-silicon validation of robust systems. In this paper, we present a new technique called Quick Error Detection (QED), which transforms existing post-silicon validation tests into new validation tests that significantly reduce error detection latency. QED transformations allow flexible tradeoffs between error detection latency, coverage, and complexity, and can be implemented in software with little or no hardware changes. Results obtained from hardware experiments on quad-core Intel® Core™ i7 hardware platforms and from simulations on a multi-core MIPS processor design demonstrate that: 1. QED significantly improves error detection latencies by six orders of magnitude, i.e., from billions of cycles to a few thousand cycles or less. 2. QED transformations do not degrade the coverage of validation tests as estimated empirically by measuring the maximum operating frequencies over a wide range of operating voltage points. 3. QED tests improve coverage by detecting errors that escape the original non-QED tests.

Post-silicon validation challenges: how EDA and academia can help

The challenges of post-silicon validation are continuously increasing, driven by higher levels of integration, increased circuit complexity, and platform performance requirements. The pressure of maintaining aggressive launch schedules and containing an increased cost of validation and debug, require a holistic approach to the entire design and validation process. Post-silicon validation is very diverse, and the work starts well before first silicon is available-for example, emulation, design-for-validation (DFV) features, specialized content development, etc. This will require enhancing pre-tape out validation to have healthier first silicon, developing more standard interfaces to our validation hooks, developing more predictive tools for circuit and platform simulation and post-silicon debug, adding more formal coverage methods, and improving survivability to mitigate in-the-field issues. We view the Electronic Design Automation (EDA) industry as a key enabler to help us bridge the gaps between pre-silicon and post-silicon validation, and extend the considerable intellectual wealth in pre-silicon tools to the post-silicon validation area.

Quick detection of difficult bugs for effective post-silicon validation

We present a new technique for systematically creating postsilicon validation tests that quickly detect bugs in processor cores and uncore components (cache controllers, memory controllers, on-chip networks) of multi-core System on Chips (SoCs). Such quick detection is essential because long error detection latency, the time elapsed between the occurrence of an error due to a bug and its manifestation as an observable failure, severely limits the effectiveness of existing post-silicon validation approaches. In addition, we provide a list of realistic bug scenarios abstracted from “difficult” bugs that occurred in commercial multi-core SoCs. Our results for an OpenSPARC T2-like multi-core SoC demonstrate: 1. Error detection latencies of “typical” post-silicon validation tests can be very long, up to billions of clock cycles, especially for bugs in uncore components. 2. Our new technique shortens error detection latencies by several orders of magnitude to only a few hundred cycles for most bug scenarios. 3. Our new technique enables 2-fold increase in bug coverage. An important feature of our technique is its software-only implementation without any hardware modification. Hence, it is readily applicable to existing designs.

Effective Post-Silicon Validation of System-on-Chips Using Quick Error Detection

This paper presents the Quick Error Detection (QED) technique for systematically creating families of post-silicon validation tests that quickly detect bugs inside processor cores and uncore components (cache controllers, memory controllers, and on-chip interconnection networks) of multicore system on chips (SoCs). Such quick detection is essential because long error detection latency, the time elapsed between the occurrence of an error due to a bug and its manifestation as an observable failure, severely limits the effectiveness of traditional post-silicon validation approaches. QED can be implemented completely in software, without any hardware modification. Hence, it is readily applicable to existing designs. Results using multiple hardware platforms, including the Intel® Core™ i7 SoC, and a state-of-the-art commercial multicore SoC, along with simulation results using an OpenSPARC T2-like multicore SoC with bug scenarios from commercial multicore SoCs demonstrate: 1) error detection latencies of post-silicon validation tests can be very long, up to billions of clock cycles, especially for bugs inside uncore components; 2) QED shortens error detection latencies by up to nine orders of magnitude to only a few hundred cycles for most bug scenarios; and 3) QED enables up to a fourfold increase in bug coverage.

Maximum clock frequency distribution model with practical VLSI design considerations

A previous model derivation of the maximum clock frequency (FMAX) distribution for a VLSI design is reviewed to enable pre-silicon predictions of frequency bins and process/design optimization for specific product targets. Model projections were compared with measured FMAX data for a 0.25/spl mu/m microprocessor. In this paper, an additional comparison is performed with a 0.13/spl mu/m microprocessor, illustrating the close agreement between the simulated and measured distributions in mean, variance, and shape for different values of temperature and supply voltage. The previous model revealed that within-die variations primarily reduce the mean FMAX, or reciprocally, increase the mean of the maximum critical path delay (T/sub cp,max/) distribution. In this paper, a closed-form analytical equation of the T/sub cp,max/ mean increase is derived as an extension to the FMAX distribution model, which further elucidates the dependency on within-die variations. For a given set of process- and circuit-level parameters, this model provides insight into the delay guard-band required to achieve specific performance goals. Moreover, the model identifies the point of diminishing returns for redesigning critical paths in the tail of the timing histogram. To explore the region of validity, a model assumption for the shape of the critical path delay distribution is examined to guide practical VLSI design decisions.

Programmable analog device array (PANDA): a platform for transistor-level analog reconfigurability

The design and development of analog/mixed-signal (AMS) ICs is becoming increasingly expensive, complex, and lengthy. Lacking a reconfigurable platform, analog designers are denied the benefits of rapid prototyping, hardware emulation, and smooth migration to advanced technology nodes. To overcome these limitations, this work proposes a new approach that maps any AMS design problem to a transistor-level reconfigurable vehicle, thus enabling fast validation and a reduction in post-Silicon bugs, and minimizing design risk and costs. The unique features of the approach include: (1) transistor-level programmability that emulates each transistor behavior in an analog design, reproducing the system and achieving very fine granularity of reconfiguration; (2) programmable switches that are treated as a design component during analog transistor mapping, and optimized with the reconfiguration matrix; (3) parasitics reduction that leverages the aggressive scaling of CMOS technology. Based on these principles, a digitally controlled PANDA platform is designed at a 32nm node. Several 90nm analog blocks are successfully emulated with the 32nm platform, including a folded-cascode operational amplifier, a sample-and-hold module (S/H), and a voltage-controlled oscillator (VCO). A solid basis to future efforts on the architecture, hierarchical optimization, and related design automation tools is demonstrated.

Programmable ANalog Device Array (PANDA): A Methodology for Transistor-Level Analog Emulation

The design and development of analog/mixed-signal (AMS) integrated circuits (ICs) is becoming increasingly expensive, complex, and lengthy. Rapid prototyping and emulation of analog ICs will be significant in the design and testing of complex analog systems. A new approach, Programmable ANalog Device Array (PANDA) that maps any AMS design problem to a transistor-level programmable hardware, is proposed. This approach enables fast system level validation and a reduction in post-silicon bugs, minimizing design risk and cost. The unique features of the approach include: 1) transistor-level programmability that emulates each transistor behavior in an analog design, achieving very fine granularity of reconfiguration; 2) programmable switches that are treated as a design component during analog transistor emulating, and optimized with the reconfiguration matrix; and 3) compensation of ac performance degradation through boosting the bias current. Based on these principles, a digitally controlled PANDA platform is designed at 45 nm node that can map AMS modules across 22-90 nm technology nodes. A systematic emulation approach to map any analog transistor to 45 nm PANDA cell is proposed, which achieves transistor level matching accuracy of less than 5% for ID and less than 10% for Rout and Gm. Circuit level analog metrics of a voltage-controlled oscillator (VCO) emulated by PANDA, match to those of the original designs in 22 and 90 nm nodes with less than a 5% error. Several other 90 and 22 nm analog blocks are successfully emulated by the 45 nm PANDA platform, including a folded-cascode operational amplifier and a sample-and-hold module (S/H).

A hybrid electrical-behavioral modeling approach for pre- and post-silicon electrical validation

This paper discusses pre- and post-silicon electrical validation requirements for highly integrated designs and highlights the need for large-scale modeling and simulation of analog components in the context of validation. Current fast SPICE tools and Analog-Mixed Signal simulation do not provide the speed and scalability necessary to perform full cluster or system-level verification of high-speed IO links or to perform a variability analysis of these circuits. This paper outlines a method to scale the simulation of these circuits with correct accounting of voltage and temperature fluctuations, within-die and die-to-die variations, and platform uncertainty, with little loss in accuracy. The results are illustrated on a self-biased PLL example and illustrate the tremendous speedup that can be achieved while maintaining a comparable accuracy to SPICE for the behaviors that are modeled.

Overcoming post-silicon validation challenges through quick error detection (QED)

Existing post-silicon validation techniques are generally ad hoc, and their cost and complexity are rising faster than design cost. Hence, systematic approaches to post-silicon validation are essential. Our research indicates that many of the bottlenecks of existing post-silicon validation approaches are direct consequences of very long error detection latencies. Error detection latency is the time elapsed between the activation of a bug during post-silicon validation and its detection or manifestation as a system failure. In our earlier papers, we created the Quick Error Detection (QED) technique to overcome this significant challenge. QED systematically creates a wide variety of post-silicon validation tests to detect bugs in processor cores and uncore components of multi-core System-on-Chips (SoCs) very quickly, i.e., with very short error detection latencies. In this paper, we present an overview of QED and summarize key results: 1. Error detection latencies of “typical” post-silicon validation tests can range up to billions of clock cycles. 2. QED shortens error detection latencies by up to 6 orders of magnitude. 3. QED enables 2- to 4-fold improvement in bug coverage. QED does not require any hardware modification. Hence, it is readily applicable to existing designs.