Nahid Mirzaie

Automatic Design and Yield Enhancement of Data Converters

Data converters play a key role in modern analog/mixed-signal systems. Accordingly, it is important to investigate their performance and yield under uncertain parameters over the design process. An efficient approach for automatic design and yield enhancement of data converters is presented. The proposed algorithm generates a general netlist for each data converter and improves transistor sizing to reach acceptable values for performance parameters with an evolutionary process, and finds the best yield simultaneously. The applied framework on two data converter structures demonstrates a reliable circuit with optimum performance, power consumption, and area overhead over a single evolutionary process in 0.18μm technology.

Yield‐aware sizing of pipeline ADC using a multiple‐objective evolutionary algorithm

Summary In this paper, an efficient and highly accurate algorithm for yield-aware design of pipeline analog to digital converters (ADCs) based on a four-step approach is presented. First, a general netlist is generated for the data converter building blocks. Then, using an evolutionary method, its best performance sizing is estimated. Finally, the yield gets enhanced to reach a desired value. With the same accuracy, the presented algorithm can achieve yield optimization by approximately five times less computational cost compared with a state-of-the-art MC-based method. The framework is applied to demonstrate a reliable converter with optimum performance, power consumption, speed and area overhead during a single running process. A prototype 10-bit resolution, 10-MS/s pipeline analog to digital converter has been simulated in a 0.18-µm 1.8-V CMOS process. Presented results, applying the proposed method, show important advantages in terms of accuracy and efficiency. Copyright