Nainesh Agarwal

FSMD Partitioning for Low Power Using ILP

It is well known that significant power savings can be obtained by disabling or shutting down parts of a circuit during idle periods. One method is to use a high level partitioning technique which considers both the controller and the datapath together. The FSMD is split into two or more simpler communicating processors. These separate processors can then be clock gated or power gated to achieve dramatic power savings since only one processor is active at any given time. Here, we propose a technique to efficiently partition a FSMD for power gating using an integer linear programming (ILP) approach. Implementing and analyzing a sample circuit shows that up to 41% static and dynamic power savings are possible. We then develop a framework to estimate the potential power savings. Using several sample circuits, the estimation framework shows that up to 69% static power savings and 30% dynamic power savings can be expected.

Automated power gating of registers using CoDeL and FSM branch prediction

In this paper, we use the CoDeL hardware design platform to analyze the potential and performance impact of power gating individual registers. For each register, we examine the percentage of clock cycles for which they can be powered off, and the loss of performance incurred as a result of waiting for the power to be restored. We propose a static gating method, with very low area overhead, which uses the information available to the CoDeL compiler to predict, at compile time, when the registers can be powered off and when they can be powered on. Static branch prediction is used in the compiler to more intelligently traverse the finite state machine description of the circuit to discover gating opportunities. We compare this static CoDeL based gating method to a dynamic, time-based technique. Using the DSPstone benchmark circuits for evaluation, we find that CoDeL with backward branch prediction gives the best overall combination of gating potential and performance, resulting in 22% bit cycles saved at a performance loss of 1.3%. Compared to the dynamic time-based technique, this method gives 52% more power gated bit cycles, without any additional performance loss.

Power efficient rapid hardware development using CoDel and automated clock gating

We present a platform for rapidly developing power efficient hardware architectures. We have developed a new language, called CoDeL, which allows hardware description at the algorithm level, and thus dramatically reduces design time. We have extended CoDeL to automatically insert clock gating at the behavioral level to reduce dynamic power dissipation in the resulting architecture. This is, to our knowledge, the first hardware design environment that allows an algorithmic description of a component and yet produces a power aware design. To estimate the power savings, we have developed an estimation framework, which is shown to be consistent with the power savings obtained using statistical power analysis using Synopsys tools. To evaluate our platform we use the CoDeL implementation of a two-dimensional discrete wavelet transform using the lifting technique. A simulation based power analysis on the designed circuit shows that CoDeLs clock gating reduces the power dissipation by up to 80%

Rapidly prototyping DSP extensions using CoDeL: the DWT using lifting

In this report, we present CoDeL, a rapid hardware prototyping language, to implement a DSP module which performs the biorthogonal one-dimensional discrete wavelet transform using the lifting technique. Specifically, we implement the wavelet transform using the Le Gall integer-to-integer 5/3 filter bank. Using CoDeL, we show how this wavelet transform can be implemented with just a few lines of code

Using CoDeL to Rapidly Prototype Network Processsor Extensions

The focus of this work is on techniques that promise to reduce the message delivery latency in message passing environments, incuding clusters of workstations or SMPs. We are introducing Network Processing extensions, and present a preliminary implementation using CoDeL to rapidly design and prototype these extensions.

Power efficient rapid system prototyping using CoDel: the 2D DWT using lifting

In this report, we present CoDel, a rapid hardware prototyping language, to implement a DSP module which performs the biorthogonal two-dimensional discrete wavelet transform using the lifting technique. Specifically, we implement the wavelet transform using the Le Gall integer-to-integer 5/3 filter bank. Using CoDel, we show how this wavelet transform can be implemented with just a few lines of code. We show how CoDel facilitates clock gating reducing dynamic power dissipation. We develop and use a state level power analysis framework, and determine that power savings of 16% can be expected.

Towards Automated FSMD Partitioning for Low Power Using Simulated Annealing

We propose a technique to efficiently partition a FSMD (Finite State Machine with Datapath) using a simulated annealing approach. The FSMD is split into two or more simpler communicating processors. These separate processors can then be clock gated or power gated to achieve dramatic power savings since only one processor is active at any given time. We develop a framework to estimate the potential power savings from partitioning. Using several sample circuits, the estimation framework shows that when the original machine is partitioned into two submachines, on average, 32% static power savings and 19% dynamic power savings can be expected, with a performance impact of 2%. The power savings with more than two partitions can be even higher, with a larger performance impact.

FSMD partitioning for low power using simulated annealing

It is well known that significant power savings can be obtained by disabling or shutting down parts of a circuit during idle periods. One method is to use a high level partitioning technique which considers both the controller and the datapath together. The FSMD is split into two or more simpler communicating processors. These separate processors can then be clock gated or power gated to achieve dramatic power savings since only one processor is active at any given time. Here, we propose a technique which uses simulated annealing to efficiently partition a FSMD for power gating. We use this non-linear model to partition 4 application circuits. We then develop a framework to estimate the potential power savings. The estimation framework shows that up to 69% static power savings and 30% dynamic power savings can be expected.

Towards Automated Power Gating of Registers using CoDeL

In this paper, we use the CoDeL platform to develop test circuits and analyze the potential and performance impact of power gating individual registers. For each register, we examine the percentage of clock cycles for which they can be powered off, and the loss of performance incurred as a result of waiting for the power to be restored. Using a time-based technique to determine when the registers can be turned off results in 15% bit cycles saved at a performance loss of 2%. We then propose a method, which uses the information available to the CoDeL compiler to predict when the components can be powered off. Results show that our CoDeL assisted gating scheme allows up to 58% more power gated bit cycles than the time-based technique, with similar performance loss

Improved FSMD partitioning for low power using Plackett-Burman

Finite State Machine with Datapath (FSMD) partitioning is an effective technique for isolating circuit components. The isolated components can be clock gated or power gated to achieve dramatic power savings. FSMD partitioning typically relies on a highly complex, parameterized model, making the impact of the various tunable parameters hard to understand, leading to suboptimal partitions. In this paper, we use the Plackett and Burman experiment design methodology, which provides a statistically rigorous approach, to study a technique which uses simulated annealing to efficiently partition a FSMD for power gating. A better understanding of the effects of the various parameters allows the partitioning model to be robustly tuned towards optimality.