Najath Abdul Azeez

A Multilevel Inverter Scheme With Dodecagonal Voltage Space Vectors Based on Flying Capacitor Topology for Induction Motor Drives

This paper presents a multilevel inverter topology suitable for the generation of dodecagonal space vectors instead of hexagonal space vectors as in the case of conventional schemes. This feature eliminates all the 6n ± 1 (n = odd ) harmonics from the phase voltages and currents in the entire modulation range with an increase in the linear modulation range. The topology is realized by flying capacitor-based three-level inverters feeding from two ends of an open-end winding induction motor with asymmetric dc links. The flying capacitor voltages are tightly controlled throughout the modulation range using redundant switching states for any load power factor. A simple and fast carrier-based space-vector pulsewidth modulation (PWM) scheme is also proposed for the topology which utilizes only the sampled amplitudes of the reference wave for the PWM timing computation.

A Medium-Voltage Inverter-Fed IM Drive Using Multilevel 12-Sided Polygonal Vectors, With Nearly Constant Switching Frequency Current Hysteresis Controller

In this paper, a current error space vector (CESV)-based hysteresis current controller for a multilevel 12-sided voltage space vector-based inverter-fed induction motor (IM) drive is proposed. The proposed controller gives a nearly constant switching frequency operation throughout different speeds in the linear modulation region. It achieves the elimination of 6n ±1, n = odd harmonics from the phase voltages and currents in the entire modulation range, with an increase in the linear modulation range. It also exhibits fast dynamic behavior under different transient conditions and has a simple controller implementation. Nearly constant switching frequency is obtained by matching the steady-state CESV boundaries of the proposed controller with that of a constant switching frequency SVPWM-based drive. In the proposed controller, the CESV reference boundaries are computed online, using the switching dwell time and voltage error vector of each applied vector. These quantities are calculated from estimated sampled reference phase voltages. Vector change is decided by projecting the actual current error along the computed hysteresis space vector boundary of the presently applied vector. The estimated reference phase voltages are found from the stator current error ripple and the parameters of the IM.

Low-Order Harmonic Suppression for Open-End Winding IM With Dodecagonal Space Vector Using a Single DC-Link Supply

This paper proposes a technique to suppress low-order harmonics for an open-end winding induction motor drive for a full modulation range. One side of the machine is connected to a main inverter with a dc power supply, whereas the other inverter is connected to a capacitor from the other side. Harmonic suppression (with complete elimination of fifth- and seventh-order harmonics) is achieved by realizing dodecagonal space vectors using a combined pulsewidth modulation (PWM) control for the two inverters. The floating capacitor voltage is inherently controlled during the PWM operation. The proposed PWM technique is shown to be valid for the entire modulation range, including overmodulation and six-step mode of operation of the main inverter. Experimental results have been presented to validate the proposed technique.

A Hybrid Multilevel Inverter System Based on Dodecagonal Space Vectors for Medium Voltage IM Drives

Dodecagonal (12-sided) space vector pulsewidth modulation (PWM) schemes are characterized by the complete absence of (6n ± 1)th-order harmonics (for odd n) in the phase voltages, within the linear modulation range and beyond, including overmodulation. This paper presents a new topology suitable for the realization of such multilevel inverter schemes for induction motor (IM) drives, by cascading two-level inverters with flying-capacitor-inverter fed floating H-bridge cells. Now, any standard IM may be used to get the dodecagonal operation which hitherto was possible only with open-end winding IM. To minimize the current total harmonic distortion (THD), a strategy for synchronous PWM is also proposed. It is shown that the proposed method is capable of obtaining better THD figures, compared to conventional dodecagonal schemes. The topology and the PWM strategy are validated through analysis and subsequently verified experimentally.

A Harmonic Suppression Scheme for Open-End Winding Split-Phase IM Drive Using Capacitive Filters for the Full Speed Range

Voltage source inverter (VSI)-fed six-phase induction motor (IM) drives have high 6n ± 1, n = odd-order harmonic currents. This is because these currents, driven by the corresponding harmonic voltages in the inverter output, are limited only by the stator leakage impedance, as these harmonics are absent in the back electromotive force of the motor. To suppress the harmonic currents, either bulky inductive harmonic filters or complex pulsewidth modulation (PWM) techniques have to be used. This paper proposes a harmonic elimination scheme using switched capacitor filters for a VSI-fed split-phase IM drive. Two 3-phase inverters fed from capacitors are used on the open-end side of the motor to suppress 6n ± 1, n = odd-order harmonics. A PWM scheme that can suppress the harmonics as well as balance the capacitor voltage is also proposed. The capacitor fed inverters are switched so that the fundamental voltage is not affected, and the fundamental power is always drawn from the main inverters. The proposed scheme is verified with a detailed experimental study. The effectiveness of the scheme is demonstrated by comparing the results with those obtained by disabling the capacitor fed inverters.

Design and Development of an Efficient Multilevel DC/AC Traction Inverter for Railway Transportation Electrification

This paper presents a new trend in the transportation industry to adopt the multilevel inverter-based propulsion systems and gives the design procedure of a new DC/AC three-phase six-level inverter for powering the rail metro cars. The proposed inverter is based on the multilevel converter as it possesses much lower component voltage stress compared with the pulsewidth-modulated (PWM) topologies. Space vector pulsewidth modulation (SVPWM) with back-to-back clamped diode voltage modulation operation is used to achieve voltage regulation and high efficiency at any loading condition. Zero-current-switching operation is achieved without using an auxiliary circuit, which leads to minimum switching losses. The novelty of the proposed inverter lies within the proposed control methodology, which uses a new switching pattern that guarantees a modified SVPWM to eliminate the unwanted harmonics from the output voltage. The new algorithm is developed using numerical iterative solution using the Newton-Raphson technique that was downloaded to the processor using digital signal processing developed code. The mathematical model is simple but proven to be effective. As a result, a higher operating efficiency at full load of 98.5% is achieved as compared to previous efficiency of 97%. Analytical, simulation, and experimental results of a 1500 Vdc/700 Vac 400-kW converter are presented to offer the proof of concept. The converter provides real estate savings for the train under floor layout, higher operating efficiency as well as better cost price than the conventional two-level PWM hard-switched converters.

Medium Voltage Drive for Induction Motors Using Multilevel Octadecagonal Voltage Space Vectors

Multilevel inverters with hexagonal and dodecagonal voltage space vector structures have improved harmonic profile compared to two-level inverters. Further improvement in the quality of the waveform is possible using multilevel octadecagonal (18-sided polygon) voltage space vectors. This paper proposes an inverter circuit topology capable of generating multilevel octadecagonal voltage space vectors, by cascading two asymmetric three-level inverters. By the proper selection of dc-link voltages and the resultant switching states for the inverters, voltage space vectors, whose tips lie on three concentric octadecagons, are obtained. The advantages of octadecagonal voltage space vector-based pulsewidth modulation (PWM) techniques are the complete elimination of fifth, seventh, eleventh, and thirteenth harmonics in phase voltages and the extension of linear modulation range. In this paper, a simple PWM timing calculation method is also proposed. Experimental results have been presented in this paper to validate the proposed concept.

A Three-Level Dodecagonal Space Vector-Based Harmonic Suppression Scheme for Open-End Winding IM Drives With Single-DC Supply

This paper presents a harmonic elimination technique based on a three-level dodecagonal space vector structure for open-end winding induction motor (IM) drives with a single-dc supply. Advantages of dodecagonal space vector switching and multilevel inverters are achieved with a single-dc supply. A dc supply-fed three-level flying capacitor (FC) inverter feeds active power to one end of the IM winding terminals and H-bridge connected capacitors eliminate fifth- and seventh-order harmonics from the other end. A pulsewidth modulation (PWM) technique is developed to switch the three-level dodecagonal space vectors and simultaneously control the H-bridge capacitors at 0.1445Vdc. The fifthand seventh-order harmonics are eliminated for the full modulation range of the three-level FC inverter, including the extreme 6-step operation. An increase in the linear modulation range has been achieved, resulting in improved dc bus utilization. Harmonic elimination is achieved by increasing switching frequency of the low-voltage capacitor connected H-bridge inverter; thus, switching frequency for the high-voltage dc supply-fed FC inverter is not increased. Using the proposed scheme, the instantaneous phase voltage never exceeds 2/3Vdc (maximum phase voltage applied for hexagonal space vector structure) for which the machine windings are rated. Additionally, the proposed inverter has also been shown to operate for field oriented control of the open-end winding IM drive.

Capacitance reduction in a single phase Quasi Z-Source Inverter using a hysteresis current controlled active power filter

One of the major issues in a single phase inverter topology is the 120Hz ripple which needs large decoupling capacitors. Big bulky electrolytic capacitors can be an issue in applications where compact size and high power density are requirements such as solar converter chargers. In z source inverter systems, the design of the impedance network is critical. In single phase z source inverter systems, the z-source network can get quite bulky if the second harmonic power fluctuations are not compensated. In this paper an active power filter (APF) has been analyzed for the DC side of the Quasi Z-Source Inverter(qZSI) Topology and hysteresis current control technique has been adopted to eliminate the voltage fluctuations in the DC side of the inverter. As a result the impedance network has been designed with the values as low as three phase z-source inverter systems and the capacitor values are low enough to replace the bulky capacitors by film capacitors, which in turn increases the life and power density of such inverter systems. The other advantage of this DC side APF being the control is simpler than an AC side APF.

A new single-stage high-efficiency photovoltaic(PV)/grid-interconnected dc charging system for transportation electrification

In this paper, a single stage highly efficient photovoltaic grid interconnected charging infrastructure has been designed for off-board DC charging for electric vehicles. This paper starts with the design of a single phase H-bridge quasi-z-source inverter (qZSI), component design and the pulse width modulation technique used. Then it discusses the control techniques used to control the power flow from the photovoltaic to the grid. The versatile qZSI topology has been used for the battery charging system using traditional controls to connect a 2 kW solar array to the AC grid. An EV battery charger has been then designed using the highly efficient full bridge DC-DC converter employing primary side Zero Voltage Switching (ZVS) using the LLC topology for a wide output voltage range. Finally, the simulated performances of the power flow have been shown with and without the EV battery charger.