Naji Rajai Nasri Ama

Phase-Locked Loop Based on Selective Harmonics Elimination for Utility Applications

Phase-locked loops (PLL) are widely used in power electronics equipment connected to the mains. The use of a square wave voltage-controlled oscillator instead of a sinusoidal one eliminates one multiplier, resulting in a simple PLL algorithm, suitable for low-cost processors. In spite of its simplicity, distorted grid voltages cause steady-state phase error. This paper proposes the use of a modified square waveform obtained by the selective harmonics elimination (SHE) method to solve the phase error problem. Simulation and experimental results for the steady state and the transient tests are presented to validate the proposed single-phase and three-phase SHE-PLL methods. The tests using a field-programmable gate array show that the dynamic response of the proposed method is similar to that of classical PLL, with a simpler implementation.

PLL performance under frequency fluctuation-compliance with standards for distributed generation connected to the grid

Grid frequency fluctuation from the nominal value is expected by the standards related to distributed generation (DG) and smart grid (SG) systems. The Phase Locked Loop (PLL) estimates a signal synchronized with the fundamental frequency of the grid voltage that will be used by the controllers of the power converter of a DG system. A discrete model for the PLL, including the phase detector harmonic generation, is proposed. Poor low pass filtering of the PLL phase detector output signal can lead to PLL output distortion and slow time response. This paper analyses and compares the operation of moving average (MAV) filters, and two strategies of adaptive MAV filters, proposed in the literature, under frequency variation. The PLL controller and its tuning presented in these papers are also discussed. An improved PLL based on adaptive MAV filter and a better tuned controller is presented. Simulation and experimental results are provided.

Leakage current minimization techniques for single-phase transformerless grid-connected PV inverters — An overview

This paper presents an overview about techniques employed to minimize the leakage current in single-phase transformerless grid-connected PV inverters, using topologies derived from the full-bridge voltage source inverter (VSI). Some representative topologies and common mode (CM) filter implementations are presented. Among the analyzed solutions, a CM filter integrated to the harmonics filter, applied to a conventional full-bridge converter with unipolar output voltage, represents a promising solution, confirmed by simulation and experimental results. Additionally, discussions about safety standards and analysis of leakage current production mechanism are presented.

Robust control design for the voltage tracking loop of a DVR

The Dynamic Voltage Restorer (DVR) is a solution for protection of sensitive loads from voltage sags and swells. Its basic function is to inject voltages in the grid line in order to mitigate voltage sags and/or swells. Typically the controller structure for a DVR is composed by an inner current loop and an outer voltage loop. Usually a proportional or proportional integral controller is used for the current loop and a resonant controller is used for the voltage loop. This paper presents the design of a robust controller for the voltage tracking loop of a DVR that guaranties the robust stability against load parameters variation, and assures the tracking of a sinusoidal voltage waveform and the rejection of the non linear load current influence with a pre specified error. The voltage controller design is based on H8 parameter specification approach. All the performance and robustness requirements are specified and analyzed based on the frequency response plot of closed loop transfer function. The proposed controller performance is validated by using PSIM software simulation and by experiments carried out on a DVR.

Implementation aspects of adaptive window moving average filter applied to PLLs — Comparative study

New standards for grid connected distributed generation systems requires operation for variable grid frequency. This paper discusses implementation details for the adaptive MAV (moving average) filter, used as a low pass filter in PLLs. The implementation of the MAV filter buffer is discussed, including the linear and circular cases, with fixed and variable window size. For this last case, a buffer that avoids data loss is shown. Details on the calculation of the mean value to avoid cumulative errors are presented. Experimental results validate the proposed strategies to reduce the PLL phase error and decrease its processing time are presented.

Optimized tuning method of stationary frame Proportional Resonant current controllers

This paper presents an optimized tuning method of Proportional Resonant (PR) current controllers implemented in the stationary frame. The approach consists of defining three operation regions based on behavior of the closed loop poles, and of determining simplified tracking and disturbance transfer functions for each of these regions. Charts of proportional and resonant normalized gains versus settling time and overshoot are then built, allowing the designer to easily visualize the influence of these gains on the transient response. It is shown that the disturbance response performance is more significant than the tracking one, and that minimum settling time and overshoot for this case are obtained if the resonant gain is set equal to the controller resonant frequency, providing a simple and efficient rule-of-thumb for the designer. Simulation and experimental results are presented to validate the method.

Disturbance calculation based on space vector dot product: Applications to compensators

The ability to individually extract the many disturbances of the AC line currents or voltages is desirable for reference signal calculation algorithms employed in power conditioners, allowing improved utilization of the power converter. This paper proposes a novel algorithm based on the dot product of three dimensional space vectors in the abc coordinate system, for real time calculation of the instantaneous positive, negative and zero sequence components for each individual harmonic. It is presented the functionalities for compensating fundamental reactive power, selected current harmonics and current unbalances. This method is computationally simple and requires no coordinate transformation. The proposed algorithms are validated by simulation and experiments.

Interactive Power Electronics Tool for Undergraduate Laboratories and Research Purposes

This research proposes the use of hardware emulation for inverter plants for the first time. This results in a new low cost, safe and robust solution for teaching control strategies for power electronics inverter circuits, composed of a digital controller (DSP or FPGA) connected to the inverter “hardware emulation circuit”. The inverter dynamical behavior is emulated by cheap operational amplifiers circuits, in such way that the student can safely measure the inverter emulated currents/voltages. The hardware emulation is not beneficial only for educational purposes but can be used for scientific research, testing and fault diagnosis of inverter systems. Substantial part of the control software development and tests can be safely and comfortably done at an office desk, without the high costs, risks and safety measures required for manipulating a real scale inverter.