Nalini C. Iyer
B.V.B. College of Engineering and Technology
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Publication
Featured researches published by Nalini C. Iyer.
ieee india conference | 2006
Nalini C. Iyer; P.V. Anandmohan; D.V. Poornaiah; V.D. Kulkarni
Reprogrammable devices such as field programmable gate arrays (FPGAs) are highly attractive options for hardware implementations of encryption algorithms. This paper proposes compact, memory less, high-speed hardware architectures for the Rijndael AES encryptor/decryptor, with combined data path, resource sharing and logic optimization for novel networking applications. Architectural optimization exploits the strength of pipelining, loop unrolling and sub-pipelining. Speed is increased by processing multiple rounds simultaneously at the cost of increased area. Algorithmic optimization exploits algorithmic strength inside each round unit. Various methods such as resource sharing and common sub expression elimination method for realizing various transformations in each round unit are presented to reduce the critical path and area issues between encryptor, and decryptor, advantage of sub-pipelining can be further explored by eliminating the unbreakable delay incurred by look-up tables in the conventional approaches, the widely used implementation of S-box, which uses combinational logic only. We explore the use of subfield arithmetic for efficient implementations of Galois Field arithmetic such as multiplication and inversion. Our technique involves mapping field elements to a composite field representation and a representation technique which minimizes the computation cost of the relevant arithmetic. Our method results in a very compact and fast gate circuit for Rijndael encryption and decryption. The pipelined architecture can be made to toggle between the encryption and decryption modes without the presence of any dead cycle. Using the proposed architecture, a fully sub-pipelined AES-128 core with both inner and outer round pipelining and a 5 sub-stages in each round unit implemented using Virtex-E devices can achieve a throughput of 26.64 Gbps at 206.84 MHz and 11720 CLB Slices in non-feedback modes with reduction of reconfigurable logic area of the complete cipher by up to 30%., and S-box with 64% reduction in area, which is faster and more efficient than the fastest previous FPGA implementation known to date
advances in computing and communications | 2014
Vishwanath G. Garagad; Nalini C. Iyer
The biometric human identification technique based on the iris of an individual is well suited in providing authentication features for any system that demands high security. This paper examines a novel technique for implementation of Iris Identification in biometric systems that is invariant to distance and tilt variations. The methodology explains relative normalization to compensate the variations and radial trace for feature extraction. Unique binary signature code for every iris is generated.
international conference on industrial and information systems | 2010
Nalini C. Iyer; Deepa; P.V. Anandmohan; D.V. Poornaiah
In this paper, compact architectures for AES Mix Column and its inverse is presented to reduce the area cost in resulting AES implementation. In the hardware implementation of AES with direct mapping substitute byte optimization, MixColumn/Inverse MixColumn transformation demands the utilization of logic resources and then effects the critical path delay and resulting throughput. The proposed MixColumn/Inverse MixColumn design based on byte and bit-level decomposition leads to two types of architecture which demonstrates deeper resource sharing within byte and between bytes and rearrangement of output terms with respect to FPGA architecture in bit level resply. The proposed architectures have been investigated on a FPGA based implementation platform. Application of the proposed architectures resulted in reduction of reconfigurable logic area by 40% as compared to separate implementation of MixColumn and Inverse MixColumn reduction and also path delay by 9% resply. Experimental results show that our proposed architecture can reduce the area cost significantly and compared with other previous implementations reported so far.
2016 IEEE International Conference on Current Trends in Advanced Computing (ICCTAC) | 2016
Sandeep S. Patil; Shreya Gudasalamani; Nalini C. Iyer; Vishwanath G. Garagad
Iris recognition system is the secure authentication tool to control access to physical assets based on iris texture. It is the most reliable biometric system because of its uniqueness and stability over time, even the genetically identical twins have different Iris textures. This paper presents a system that is immune to tilt and scale variations. The iris region of interest is segmented based on selective cropping. Scale variation is compensated during normalization by fixing the pupil radius. A novel technique has been proposed to compensate for tilt variations. Template matching is performed by bit to bit comparisons.
Journal of Engineering Education Transformations | 2016
M. Kaushik; Satish Chikkamath; Nalini C. Iyer
The proposal describes about a course activity designed for sixth semester students of Instrumentation Technology for the course Process Control and Automation. As the activity demands technical, writing and oral presentation skills, students were accordingly grouped based on their capabilities they possess which in turn helps to enhance the other skills they lack. The activity designed focuses on identification and study of programmable logic controllers (PLCs) required in the field of automation, deployment of automation concepts for development of ptototypes and usage of virtual instrumentation tool for implementation of controller principles. This activity has positive effect on personal and interpersonal development of students as well between peer communities. Progress justification can be made by mapping the performance indicators formed for the evaluation of activity with the attainment of program outcomes.
Journal of Engineering Education Transformations | 2016
M. Kaushik; Nalini C. Iyer
The proposal describes about a course activity designed for fifth semester students of Instrumentation Technology for the course Process Instrumentation. The quantifiable short term outcome of the acitivity is to propose a sensor model with new operating principle. Student undergoes phases of field exercise, lab experimentation, literature survey that helps in proposing a sensor model. Course activity has been designed to address exploratory learning, better communication skills and industrial perspective of the course. Thus strengthening Process Automation vertical at program level. This progress justification can be made by mapping the rubrics formed for the evaluation of activity with the attainment of program outcomes.
2016 IEEE 4th International Conference on MOOCs, Innovation and Technology in Education (MITE) | 2016
Satish Chikkamath; Nagaraj Vannal; R. M. Shet; P. C. Nissimgoudar; Nalini C. Iyer
There is a need to prepare engineering students for the future world to be good engineers, to be a good engineer the theoretical background of the curriculum that they go through is not sufficient they need to practice what they have understood. In order for students to practice as engineers, they need to have exposure to a number of projects that offer complex problems, along with the uncertainty of factors that influence such problems. In this view Electronic instrumentation program is divided into two verticals embedded system and process automation to provide domain specific Knowledge to students and courses are designed to fit into these domains to satisfy current industrial needs. To provide more hands on experience curriculum and related activities are planned at three different levels. At first level(Second year) along with laboratory course, activities are planned and defined as course projects which augments theoretical concepts and also aids in interconnecting various courses for integrated approach, these activities strengthen the conceptual knowledge of students. Next level (Third year) theme based Mini and Minor projects are planned, themes are decided based on Subject learnt in previous semester and recent technological developments. These activities provide a platform to realize applications belonging to a specific theme. In the final level capstone projects are grouped into Industry projects, product development and research oriented projects. Students are allowed to extend their academic experience into areas of personal interest, working with new ideas, issues, organizations, and individuals. These activities helped students to develop their communication, interpersonal, project management, and design skills. It also provides students with an understanding of the economic, financial, legal, and regulatory aspects of the design, development, and commercialization of the technology with these activities carried out throughout the year we are able to achieve better quality in paper publications, winning awards in prestigious project competitions conducted by industries and academia along with improvement in placements, Semester End Examination and addressing professional and technical outcomes of ABET.
Archive | 2015
P. C. Nissimagoudar; Nalini C. Iyer; B. L. Desai; M. Uma; C. D. Kerure; Venkatesh Mane; M. R. Kiran; Ramakrishna Joshi
Automotive electronics is a course that requires skills from multiple disciplines including, but not limited to, mechanical, control, computer science, and electronics. The course is introduced to address the needs of embedded and automotive industries, hence providing the necessary knowledge and skills required for those industries. The objective of the curriculum is to enhance learning and improve student’s implementation skills. In this paper, we propose to introduce the exercises including real-world case studies and experiential learning. The major challenge of teaching this course was to teach mechanical concepts for electrical science students and to develop electronics for mechanical systems. The practical demo sessions by automobile labs gave the desired foundation for the course. The engine management concepts were taught using a very popular simulation software, AT Electronics tool, which is a combination of electronics and diagnostics. This activity gave a real feel of engine management systems to learn how complex systems work and to diagnose faults with them. The paper also discusses another major activity in the form of course projects. The course projects resulted in the application of domain knowledge and improvement of skills by using appropriate tools. In addition to these activities, all regular classes included animations and video presentations to make the concepts clearer. Special lectures by industry experts were also arranged to give the students a wide perspective of the subject. The paper discusses the impact of these activities in the form of student feedback, placement results, and participation in technical events. This experiential learning helped the students to improve comprehensive application ability and innovative consciousness.
Journal of Engineering Education Transformations | 2015
P. C. Nissimagoudar; Venkatesh Mane; Nalini C. Iyer; S. Ramakrishna; M. R. Kiran; K. M. Uma; A. B. Raju; Anisha W. Joseph; K. Hemanthraj; B. L. Desai; Ashok Shettar
The paper explores the new technology commercialization model being followed at The University of Akron (UA).UA has implemented the National Science Foundation (NSF)Innovation ICorpsTMmodel since 2013. This paper describes how the NSF I-Corps model has changed the innovation culture at UA and allowed the academic faculty to explore the business potential of their intellectual property.Differences in implementation across several I-Corps Sites are explored. The lessons from UAs experience show that the I-Corps Sites program has been a resounding success and helped faculty and students to become more entrepreneurial in exploring the commercial value and demand drivers of technologies invented at UA.Students are more attracted towards and enthusiastic about modern teaching techniques. This paper provides a new concept in the design of a coursework thus enabling the teachers to enhance the teaching and learning process. The course work, laboratory and course projects are linked through proper planning. It is observed that there is an increase in the degree of involvement of the students in the course and they move from doing demonstrations to structured enquiry and also open ended enquiry. This new framework can also address some of the ABET criteria effectively. Results show positive response from the students towards this new technique.The real time experience of Signals and Systems has been embedded in the form of mathematical expressions. The learners fi nd diffi culty in applying these mathematical concepts in a real time scenario. This paper presents the details of effective learning technique attempted for the Signals and Systems course at the under graduate engineering program using mind mapping. Mind mapping as a technique tests the students ability for interactive learning to improve retention and reduce revision time. This paper discusses about the effects of digital/ paper-based mind mapping over conventional teaching method to shift an teaching centric to learning centric. This learning not only focuses on retention of concepts but also caters to the generation of ideas required for solving an engineering problem, which in turn improves the writing skills of the students. Findings showed that there was a signifi cant positive difference in students academic achievement and attitude towards learning the subject through the paper/digital based mind mapping.
international conference on computing for sustainable global development | 2016
Shivaji Kulkarni; Shrihari Durg; Nalini C. Iyer