Nam-Jin Oh

CMOS Direct-conversion Radio Transceiver Design for 5-GHz WLAN Applications

Abstract Direct-conversion radio transceiver chipsets for 5-GHz WLAN have been implemented in 0.18-/jm CMOS technology. The receiver front-end includes low flicker noise down-conversion mixers where the parasitic tail capacitances in the transconductance stage are resonated out at the operating frequency. To reduce the local oscillator pulling and leakage, an offset clock generator is implemented in which a voltage controlled oscillator operates at two-thirds of the operating frequency band. The transmitter front-end can drive up to 2 dBm output power at the driver amplifier. The receiver front-end has 6.5 dB noise figure, -13 dBm input IP3, and voltage gain of 20 dB. The overall receiver has voltage gain of 60 dB. The phase noise of the clock generator at 5 GHz frequency is -109 dBc/Hz at 1 MHz offset.

A Single-Stage Low-Power RF Receiver Front-End: Series Resonator Based LMV Cell

ABSTRACT This paper proposes a novel low-power merged low noise amplifier (LNA), mixer, and voltage-controlled oscillator (VCO) called LMV cell exploiting a series LC (SLC) resonator. In contrast to the conventional parallel LC (PLC) resonator, the SLC resonator plays the role of enhancing the voltage swing at the series LC connection node which is cross coupled to the gate of the VCO switching transistors. The low intermediate frequency or baseband signal can be directly sensed at the drain nodes of the VCO switching transistors by adding simple resistor–capacitor (RC) filters. Using a 65-nm complementary metal-oxide semiconductor (CMOS) technology, the proposed LMV cell is optimized for the phase noise performance, and compared to the performance of the Liscidinis LMV cell which stacks the LNA, mixer, and VCO exploiting a PLC resonator. Compared to the Liscidinis LMV cell, the proposed LMV cell has larger voltage gain and better phase noise performance for the same dc power dissipation. While the simulated phase noise of the Liscidinis LMV cell is −47.8, −75.7, and −100.3 dBc/Hz, the phase noise of the proposed LMV cell is −71.2, −92.8, and −113 dBc/Hz at 10 kHz, 100 kHz, and 1 MHz offset frequency, respectively. The simulated voltage conversion gain of the Liscidinis LMV cell and the proposed LMV cell is 20 and 30 dB, respectively. Both LMV cells consume 0.35 mW dc power from a 1-V supply.

An Ultra-Low Phase Noise CMOS VCO Design Technique for Mobile Applications

ABSTRACT This paper describes an ultra-low phase noise complementary metal-oxide semiconductor (CMOS) voltage-controlled oscillator (VCO) design technique targeted for GSM 900 and DCS 1800 base station (BTS) receiver, which require the toughest phase noise performance between 600 kHz and 3 MHz offset frequency. The proposed VCO suppresses the phase noise by three mechanisms; removes the current source, the main noise contributor in the VCO; includes double tuned resonators to prevent the switching pair from entering the triode region; filters out the second harmonic noise with a small size inductor at the common mode node of the VCO. The feasibility of the proposed VCO is verified using a 65 nm CMOS technology. Operating at around 3.6 GHz frequency range, the VCO is designed to meet the phase noise requirement of micro BTS and normal BTS. The proposed VCO consumes 27 mW dc power from a 0.7 V supply, and achieves the best figure-of-merit of −201dBc/Hz at 3 MHz offset.

A low-noise mixer with an image-reject notch filter for 2.4GHz applications

This paper presents a low noise first down-conversion mixer with a notch filter for the heterodyne receiver. The notch filter connected to the output node of the mixer driver stage plays a role of image rejection at an image frequency, thereby suppressing the sideband image noise and improving the mixer noise performance. Targeted for 2.4GHz industrial-scientific-medical band applications, a simple source-degenerated down-conversion single balanced mixer with the filter is implemented. The measurement results of the proposed down-conversion mixer shows about 3.0dB improvement of single-side band noise figure, about 2.9dB power conversion gain improvement, and 25dB image suppression compared to those without the filter dissipating 4mA from a 2.5V supply voltage.

A low phase-noise CMOS voltage-controlled oscillator with a series LC resonator

This paper proposes a novel phase-noise (PN) reduction technique for high performance voltage-controlled oscillator (VCO) using a cross-coupled series LC resonator, rather than parallel LC resonator. While the series connected inductor and capacitor enhances the fundamental frequency swing at the LC connection node, it gives a cleaner spectral purity output and suppresses the overall noise at the drain node of the cross-coupled switching cell. The proposed technique is verified using a 65 nm CMOS process with the VCO operating at around 3.6 GHz frequency range. The phase noise of the VCO is -122.4 dBc/Hz, -125.0 dBc/Hz, and -136.7 dBc/Hz at 600 kHz, 800 kHz, and 3 MHz offset frequencies, respectively, which satisfy the stringent phase noise requirements such as GSM standards operating at 900-MHz, 1800-MHz and 1900-MHz band. The proposed VCO consumes 5.6 mW dc power from a 1-V supply.

A switchable quadband LNA for mobile wireless communications exploiting varactor tuning

A low-power switchable quad-band CMOS LNA for PCS(1.8 GHz), WCDMA(2.1 GHz), WiBro(2.3 GHz), and LTE(2.6 GHz) applications is presented. The proposed LNA has an advantage of occupying less chip area compared to other concurrent topology which uses more inductors by adopting LC tank resonators. Also, it consumes less current compared to other topology which adopts a switched parallel transistor technique. The proposed LNA is designed using a 0.18-µm CMOS technology. The LNA core draws only 2.6 mA from a 1 V supply voltage. The S11 and S22 of the proposed LNA are less than −10 dB in the four frequency bands. The noise figure is less than 3.5 dB. The power gain is larger than 20 dB.