Nam-Soo Kang

Variable V/sub CC/ design techniques for battery-operated DRAMs

Wide-voltage-range DRAMs with extended data retention are desirable for battery-operated or portable computers and consumer devices. The techniques required to obtain wide operation, functionality, and performance of standard DRAMs from 1.8 V (two NiCd or alkaline batteries) to 3.6 V (upper end of LVTTL standard) are described. Specific techniques shown are: (1) a low-power and low-voltage reference generator for detecting V/sub CC/ level; (2) compensation of DC generators, V/sub BB/ and V/sub PP/, for obtaining high speed at reduced voltages; (3) a static word-line driver and latch-isolation sense amplifier for reducing operating current; and (4) a programmable V/sub CC/ variable self-refresh scheme for obtaining maximum data retention time over a full operating range. A sub-50-ns access time is obtained for a 16 M DRAM (2 M*8) by simulation. >

A pulse-tuned charge controlling scheme for uniform main and reference bitline voltage generation on ITIC FeRAM

In order to improve cell array efficiency and reference voltage characteristics of ITlC FeRAM, two key techniques are proposed in this paper. 1) Cell operation scheme with pulse-tuned signals on wordline and plateline for achieving uniform bitline levels in short time and 2) reference voltage generation scheme using dual pulse control for reference voltage to track variable bitline sensing voltage in wide range of operation voltage and temperature. 2Mb ITlC FeRAM in unit block of 512 rows by 256 columns cell array with 0.35pm design rule are implemented. The optimized uniform bitline sensing voltage and reference voltage are achieved at the condition of the first wordline pulse signal of 3011s and the reference dual pulse signal time of 30-4011s at 3V in room temperature.

Variable V/sub cc/ design techniques for battery operated DRAMs

The authors describe a variable V/sub cc/ design technique to extend battery life. Several special circuits for low V/sub cc/, compensated DC generators and wordline drivers are proposed. These are implemented in a 16 M DRAM using 1 polycide, 3 poly, double-metal, and stacked capacitor based 0.4 mu m CMOS technology. The simulated speed of V/sub cc/ variable design is compared with conventional design at 25 degrees C. The slowdown below 2 V is due to threshold voltage and transistor characteristics.<<ETX>>

Advanced bus system interface (ABSI) LCD module

Abstract— Samsung has successfully developed the worlds first notebook panel based on Advanced Bus System Interface (ABSI) technology. ABSI is a new architecture which uses a point-to-point topology, serial gamma reference distribution, current-mode interface, and chip-on-glass (COG) technology to deliver a high-performance low-emission minimal-interconnect 8-bit-capable cost-effective LCD module in the smallest possible form factor. The first model is a 12.1-in. WXGA panel designed to work in an ultra-slim notebook application. This model combines ABSI technology with a-Si integrated gate drivers, resulting in the most advanced notebook panel manufactured to date.