Nam-Yeun Kim

Systolic architectures for inversion/division using AB 2 circuits in GF(2 m )

The current paper presents a new AB2 algorithm based on the MSB-first scheme using a standard basis representation of Galois fields, GF(2m). Thereafter, parallel-in parallel-out and serial-in serial-out systolic realizations for computing AB2 and inversion/division in GF(2m) are proposed on the basis of the new algorithm. The resulting architectures have a low hardware complexity and small latency when compared to conventional approaches. Furthermore, since the proposed architectures incorporate simplicity, regularity, modularity, and pipelinability, they are well suited to VLSI, produce a maximum throughput performance, and can also be utilized as the basic architecture for a cryptoprocessor.

Digit-Serial AB 2 Systolic Array for Division in GF(2 m )

Digit-serial architecture is an attractive solution for systems requiring moderate sample rate and where area and time consumption are critical. The current paper presents a digit-serial-in-serial-out systolic architecture for performing an AB2 operation in GF(2 m ). If the appropriate digit-size is selected, the proposed method can meet the throughput requirement of a specific application with minimum hardware. And, the area-time complexity of the pipelined digit-serial AB2 systolic architecture is approximately 10.9% lower than that of the nonpipelined version when m = 160 and L = 2. Based on the new AB2 digit-serial architecture, we also proposed a digit-serial systolic for inverse/divisions. Furthermore, since the proposed architectures are simplicity, regularity, modularity and pipelinability, they are well suited to VLSI, and can also be utilized as the basic architecture for a cryptoprocessor.

Montgomery multiplication and squaring algorithms in GF(2 k )

The current paper presents a fast implementation of group-level finite field Montgomery algorithms using two look-up tables. The proposed algorithm simultaneously computes Montgomery multiplication and squaring, thereby making modular exponentiation much faster. Plus, the proposed method is more efficient than existing multipliers when considering the tradeoff of computation time for table space. The use of tables reduces the number of operations, saves time through pre-computation, and avoids the complicated computations required in the Montgomery method. Consequently, the proposed look-up table-based algorithms have the advantage of speed and are particularly suitable for cryptographic applications, where k is large, and in memory-constrained environments, such as smart cards and embedded cryptosystems.

Inversion/Division Systolic Architecture for Public-Key Cryptosystems in GF(2m)

Finite field arithmetic operations have been widely used in the areas of network security and data communication applications, and high-speed and low-complexity design for finite field arithmetic is very necessary for these applications. The current paper presents a new AB2 algorithm along with its systolic implementations in GF(2m). The proposed algorithm is based on the MSB-first scheme using the standard basis representation. In addition, parallel-in parallel-out systolic architectures are also introduced using this algorithm as a foundation. The proposed architectures have a low hardware complexity and small latency compared to conventional architectures. In particular, the hardware complexity of AB2 and inversion/division array are about 25% lower than Wangs over GF(2m), while the latency of AB2 and inversion/ division array are about 40% and 49.6% lower, respectively. Furthermore, since the proposed architectures incorporate simplicity, regularity, modularity, and pipelinability, they are well suited to VLSI implementation and can also be utilized as the basic architecture for a crypto-processor.

A Power-Sum Systolic Architecture in GF(2m)

Finite field arithmetic operations have been widely used in the areas of data communication and network security applications, and high-speed and low-complexity design for finite field arithmetic is very necessary for these applications. This paper presents a new algorithm and architecture for the power-sum operation (AB2+C) over GF(2m) using the standard basis among these finite field operations. The proposed algorithm is based on the MSB-first fashion, plus the architecture has a low hardware complexity and small latency compared to conventional approaches. In particular, the hardware complexity and latency of the proposed array are about 19.8% and 25% lower than Weis over GF(2m), respectively. In addition, since the proposed architecture incorporates simplicity, regularity, modularity, and pipelinability, it is well suited to VLSI implementation and can be easily applied to inversion architecture.

Efficient Power-Sum Systolic Architectures for Public-Key Cryptosystems in GF(2m)

The current paper presents a new algorithm and two architectures for the power-sum operation (AB2 + C) over GF(2m) using a standard basis. The proposed algorithm is based on the MSB-first scheme and the proposed architectures have a low hardware complexity and small latency compared to conventional approaches. In particular, the hardware complexity and latency of the proposed parallel-in parallel-out array are about 19.8% and 25% lower, respectively, than Weis. In addition, since the proposed architectures incorporate simplicity, regularity, modularity, and pipelinability, they are well suited to VLSI implementation and can be easily applied to inverse/division architecture.