Namsung Kim

Ultra-low NMOS contact resistivity using a novel plasma-based DSS implant and laser anneal for post 7 nm nodes

We report a record-setting low NMOS contact resistivity of 1.2×10^-9 Ωcm² compatible with Ti/Si system and dopant segregation Schottky (DSS) based solution. The ultra-low contact resistivity of Ti/Si system is demonstrated with Highly Doped Si:P Epi layer and P implantation using conformal plasma implant followed by millisecond laser anneal. Additionally, we show that short-pulse nanosecond laser as post implant anneal provides a promising pathway to further improve NMOS ρ_C to below 1×10^-9 Ωcm² for the post 7 nm nodes.

PMOS contact resistance solution compatible to CMOS integration for 7 nm node and beyond

We report a PMOS contact resistivity (pc) improvement strategy by forming Ge-rich contact interface which is compatible to Ti/Si(Ge) system and CMOS integration flow. Short pulsed (nsec) laser anneal and advanced treatment during pre-clean have shown to be effective to segregate Ge towards SiGe surface resulting in PMOS ρc improvement. With Ge% increasing from 45 to 100%, pc improved three-fold, from 1.2e-8 to 2.8e-9 Ωcm2, due to bandgap modulation and preferred Fermi-level pinning [1]. In the end, we propose a CMOS-integration-compatible contact flow which addresses ρc optimization for both PMOS and NMOS contact.

Real impact of W/WNx/Poly-Si gate stack in volume production of high density DRAM

We have investigated the feasibility for volume production of high density DRAMs employing a polymetal gate stack(W/WNx/Poly-Si). Especially, based on the fully matured production level, DRAM devices gated with polymetal stack were directly compared to those with conventional polycide stack (WSix/Poly-Si) with respect to the impact of gate etch post-cleaning and selective oxidation. Also, we proposed the best solution to overcome the critical issues related to tungsten (W) process, still keeping comparable product performance to conventional polycide gate stack.

Ultra-low (1.2×10 −9 Ωcm 2 ) p-Si 0.55 Ge 0.45 contact resistivity (ρ c ) using nanosecond laser anneal for 7nm nodes and beyond

The recent FinFET scaling for 10–7nm node has resulted in significantly reduced contact areas for source/drain regions, leading to high contact resistance (Rc) [1-3]. Hence, it has become extremely critical to reduce the contact resistivity (ρ<inf>c</inf>) to < 1×10⁻⁹Ω.cm². ρ<inf>c</inf> can be reduced by increasing the dopant concentration at the metal/semiconductor interface and by lowering the barrier height [4]. Several studies have reported improvements in NMOS ρ<inf>c</inf> for Ti-based contacts using highly doped Si:P epi and advanced implant and activation techniques [5, 6]. For TiSi<inf>2</inf> based contacts, the Schottky barrier height (SBH) for n-ype silicon is low; however, it is slightly higher for p type SiGe. Thus, there is a strong requirement to improve the PMOS ρ<inf>c</inf> when Ti based contacts are used for both NMOS and PMOS.

Suppression of Short Channel Hump of nMOSFET Using NF3-Added ILD HDP Process

Introduction As application of battery-operated machines such as handheld computer and PDAs, demands of low power DRAMs gradually show upward curye. To extend battery lifetime, subthreshold property of peripheral MOSFET is determinant factor to reduce stand-by power consumption. Although STI (Shallow Trench Isolation) process has been widely used in high density DRAM integration due to its superior isolation property, it has suffered from short channel hump of nMOSFET. Previous papers revealed that short channel hump of TMOSFET was mainly attributed to STI corner round. Also, recent literature reports that short channel hump of nMOSFET is closely related to ILD(Inter Layer Dielectric) layers. However, this is not enough to fully explain its phenomena. In this paper, its relationship of short charurel hump with ILD HDP layer is insensibly investigated and NFr-added ILD HDP process is proposed to maintain both hump-free nMOSFET and high transistor performance, for the first time.

Effect of Poly Metal Gate Etch Post-Cleaning on the Tail Distribution of DRAM Data Retention Time

Introduction As the memory density in DRAM increases, the resistance of a word line significantly increases and the gate RC delay is placing serious limitations on device performance. The use of metal gate is one of the solutions to this problem. Tungsten has been widely studied as the gate material among many other choices, due to its low resistivity and thermal stability[1-2]. However, the process incompatibility with respect to the conventional polycide gate process has been giving rise to the issue of data retention time in DRAM cells among many other device characteristics. For example, the conventional polycide gate etch post-cleaning condition (the chemical containing HrOr) followed by the metal gate patterning could not be used because it corrodes the metal layer. The cleaning process after gate etching is a necessity for effectively removing unwanted byproducts generated by gate etch process. Therefore, optimizing the cleaning condition in the poly metal gate is an important subject, associated with data retention time as well as cell transistor characteristics such as threshold voltage shift and hot carrier degradation. In this paper, we have investigated, for the first time, the effect of post-cleaning process after gate pafferning on the tail distribution of data retention time in DRAM cells having poly metal (WW-N/poly-Si) gate. And also, we propose the optimized gate etch post-cleaning condition in poly metal gate device to guarantee the characteristics of DRAM data retention time comparable to that of the conventional polycide gate etch postcleaning process.

Improvement of the tail component in retention time distribution using buffered n-implantation with tilt and rotation (BNITR) for 0.2 um DRAM cell and beyond

The novel junction process scheme in DRAM memory cell with 0.2 um design rule and STI (Shallow Trench Isolation) has been investigated to improve the tail component of DRAM retention time distribution. In this paper, we propose BNITR (Buffered N-Implantation with Tilt and Rotation) process scheme that is designed on the basis of the local field-enhancement model of the tail component and report an excellent improvement effect in tail distribution of retention time without device degradation.