Nand Kumar

Profile-driven behavioral synthesis for low-power VLSI systems

We present a profile-driven approach to behavior level synthesis. In this approach, event activities related to various operations and carriers in the behavioral specification are measured by simulating the description using user-supplied profiling stimuli. These event activities are then used during the synthesis process to estimate the switching activity in the design being synthesized. Overall switching activity estimation is based on modulating the average intrinsic switching activities of the synthesis library modules using the event activities. This estimate is used to select a module set and a schedule which, besides meeting the area and clock-speed constraints, would minimize the switching activity in the design. Experimental results for a number of examples show that the switching activity estimated during synthesis deviates by less than 10% on the average from the actual switching activity measured after completing synthesis.The same profile-driven approach is applied to estimate the total amount of capacitance that would switch in the design when the given stimuli is applied. Again, experimental results show that, on the average, the estimated switched capacitance deviates from the actual measured value by about 12%.

DSS: a distributed high-level synthesis system

DSS, a large-scale ongoing exercise in developing parallel algorithms for high-level synthesis and implementing them in an integrated distributed system to evaluate their individual and collective effectiveness, is discussed. Embedded in a very-high-speed integrated circuit hardware description language (VHDL) centered design environment, DSS consists of a collection of parallel algorithms executing on a multiple input, multiple data (MIMD) multiprocessor machine. The system uses coarse-grained parallelism to explore and evaluate many alternative VLSI designs efficiently. DSSs internal organization and its scheduling, register optimization, interconnection formation, and controller generation techniques are described. Results illustrating DSS performance with respect to design quality, and the efficiency of the DSS algorithms in a multiprocessor environment are presented.<<ETX>>

An integrated multicomponent synthesis environment for MCMs

The multicompact synthesis (MSS) integrated design environment for multichip modules (MCMs) is discussed. The MSS environment is centered in VHDL (very-high-speed integrated circuit hardware description language), WAVES (waveform and vector exchange specification), and PDL (performance description language). MSS provides four levels of automated synthesis support all the way from the behavioral level to MCM placement and routing, three levels of simulation support including behavioral, register, and switch levels, and tools for automated test-bench compilation and design validation for all synthesized designs. Three tutorial examples illustrate MSS algorithms and results. The primary example is the Find, which performs a bubble sort followed by binary search. It is used as the running example because it is small. Such small specifications, however, do not require MCMs. Two larger examples, the Move Machine and the Viper Microprocessor, are used to illustrate the results.<<ETX>>

High level profiling based low power synthesis technique

We present a profiling based technique for power estimation. This technique is implemented in the PDSS (Profile Driven Synthesis System) for the synthesis of low power designs. Initially, each module in the module library is characterized for the average switching capacitance per input vector. The input description is simulated using user-specified set of input vectors to collect the profile data for various operators and carriers. The profile data, in conjunction with the pre-characterized module library is used to estimate the total capacitance switched by each of the valid schedules produced by the PDSS scheduler. A valid schedule is one which satisfies other constants such as area and delay. The schedule with the least switching capacitance estimate is further synthesized to the layout level. Results show an average deviation of 12% compared with the actual switching capacitance values at the layout level.

Experiences in Functional Validation of a High Level Synthesis System

The goal of functional validation of a high-level synthesis system is to assert, with a reasonable degree of confidence, that the layouts generated by the high-level synthesis system correctly implement the specified behavior. This paper presents a systematic approach to functional validation based on the analysis of specification language constructs, design example formation to cover combinations of constructs, test-bench generation and automated test result comparison. We have successfully applied this approach in validating a high-level synthesis system, called DSS, which accepts specifications stated in VHDL. This effort resulted in the development of a functional validation suite consisting of 23 design examples.

Finite state machine verification on MIMD machines

The authors present a parallel algorithm for finite state machine (FSM) verification on multiple instruction/multiple data (MIMD) machines. Given two FSMs, the verification process consists of dynamically constructing the product machine and investigating the reachability of the failure state (from the start state) of the product machine in a distributed fashion. The technique partitions one of the FSMs across a set of processors by distributing the states of the FSM among the processors. Experimental results on benchmark circuits demonstrate near linear speedup.<<ETX>>

Resource constrained RTL partitioning for synthesis of multi-FPGA designs

In this paper we address the problem of partitioning register level designs for implementation on multiple FPGAs. The partitioner uses a modified multi-way Fiduccia-Mattheyses algorithm. Cost estimation functions needed by the partitioner to estimate the resources needed by the design on a FPGA have been developed. The methodology for estimation of resources on an FPGA (function generators, flip-flops and CLBs), and partitioning of the design are discussed in detail.

A profile driven approach for low power synthesis

A profile driven approach to behavioral synthesis is presented. For a given design and a set of input vectors, the switching activity in the design yields a measure of the power consumption. Every module in a parameterized module library is characterized by its average switching activity per input vector. For a given behavioral specification, simulation using user specified inputs is carried out to collect the profile data of various operations and carriers in the specification. In the performance estimation phase, the profile data with the switching activity data in the precharacterized module library is used to estimate the average switching activity of all the module sets meeting other user specified constraints such as area and delay. The module set with the least estimated switching activity is further synthesized. Experimental results show that the switching activity estimated during synthesis deviates by less than 10% on the average from the actual switching activity measured after completing synthesis.